High speed NXM bit digital, repeated addition type multiplying circuit

A high speed N.times.M bit digital, repeated addition type multiplying circuit for multiplying a N-bit multiplicand, the N.sup.th bit of which is a sign bit, by a M-bit multiplier, the M.sup.th bit of which is a sign bit, said digital multiplier comprising:

• (a) N(M+1) combining circuits mathematically arranged into M addition rows and a final carry resolution row forming N+M-1 columns, each combining circuit in the M addition rows including an AND gate having two inputs and and an output, with one input of each AND gate in a row being connected in parallel and to receive a multiplier-bit, each row receiving a different multiplier-bit, and with the other input of each AND gate being connected to receive a multiplicand-bit, each AND gate in a row receiving a different multiplicand bit;
• (b) each combining circuit, except the final, N.sup.th, sign bit combining circuit and the first row, in each of the M addition rows further including a multiply/adder cell having an input connected to the output of said associated AND gate, a sum input and output with the sum input being connected to the sum output of the combining circuit in the previous row and like column, and a carry input and output with the carry input being connected to the carry output of the combining circuit in the previous row and previous column, except for the carry inputs of the combining circuits in the second row which are connected to a common potential;
• (c) each combining circuit in the M.sup.th addition row including inverting means connected to invert the multiplicand bits prior to application to the AND gate and each of the N.sup.th bit combining circuits in the remaining addition rows including inverting means connected to invert the multiplier bits prior to application to the AND gates;
• (d) the combining circuits in the final carry resolution row each including a multiply/adder cell having a sum input connected to the sum output of the corresponding combining circuit in the M.sup.th addition row and a sum output forming a portion of the output of the digital multiplier, the first and N.sup.th combining circuits in the final carry resolution row each having an input connected to receive the N.sup.th multiplicand bit, the first combining circuit in the final carry resolution row further having an input connected to receive the M.sup.th multiplier bit, and the N-1 remaining combining circuits, excluding the first combining circuit in the final carry resolution row, each having two inputs connected to receive the carry-bit outputs from the preceeding combining circuits in the M.sup.th addition row and the final carry resolution row, respectively.

A high speed N.times.M bit digital, repeated addition type multiplying circuit on a single chip, wherein N is a number of bits representing one of the multiplier and multiplicand, M is a number of bits representing the other of the multiplier and multiplicand, and N is at least as large as M, said digital multiplying circuit comprising:

• (a) semiconductor chip;
• (b) N(M+1) combining circuits formed on said chip and mathematically arranged into M addition rows and a final carry resolution row forming N+M-1 columns and outputs;
• (c) N input terminals for the one of the multiplier and multiplicand and M input terminals for the other of the multiplier and the multiplicand, said N and M input terminals being connected to said N(M+1) combining circuits for providing repeated addition type multiplication of the multiplier and the multiplicand represented by the N and M bits;
• (d) N input pads formed on said semiconductor chip;
• (e) M clocked latch circuits formed on said semiconductor chip and having M clocked slave latch circuits formed on said semiconductor chip and associated therewith, said M clocked latch circuits being coupled to at least M of the N input pads and said M clocked slave latch circuits being coupled to said M input terminals of said combining circuits, said M clocked latch circuits receiving and latching bits from said input pads in response to clock signals applied thereto and latching the bits into said M clocked slave latch circuits in response to clock signals applied thereto;
• (f) N clocked latch circuits formed on said semiconductor chip and coupled to the N input terminals of said combining circuits and to the N input pads for receiving and latching bits from the N input pads in response to clock signals applied to said clocked latch circuits;
• and
• (g) said N clocked latch circuits and said M clocked slave latch circuits connecting the latched bits to the N and M input terminals, respectively, of the combining circuits in response to clock signals applied thereto.

In a high speed addition type arithmetic logic unit, a high speed carry propagation line comprising:

• (a) a plurality of digital adder circuits forming an addition row, each adder circuit including a carry-bit input and a carry-bit output;
• (b) said digital adder circuits each being constructed with a high speed carry propagation line between the carry-bit input and the carry-bit output including, as active elements, only pass gates;
• (c) regeneration means coupling the carry-bit outputs of predetermined ones of said plurality of digital adder circuits to the carry-bit inputs of the next adjacent ones of the plurality of digital adder circuits in the addition row, the predetermined ones of said plurality of digital adder circuits having predetermined numbers greater than one, of the plurality of digital adder circuits interspersed therebetween in the addition row with the carry-bit outputs of each interspersed digital adder circuit, except the last digital adder circuit in the addition row, being connected to the carry bit inputs of the following digital adder circuit in the addition row, and said regeneration means inverting the carry bits;
• and
• (d) alternate predetermined numbers of digital adder circuits between said predetermined ones of said plurality of digital adder circuits including means for utilizing inverted carry bits.

In a high speed addition type arithmetic logic unit, a high speed carry propagation line comprising:

• (a) a plurality of digital adder circuits forming an addition row, each adder circuit including a carry-bit input and a carry-bit output;
• (b) said digital adder circuits each being constructed with a high speed carry propagation line including, as active elements, only pass gates;
• and
• (c) regeneration means coupling the carry propagation lines of predetermined ones of said digital adder circuits in the addition row, the predetermined ones of said plurality of digital adder circuits having predetermined numbers, greater than one, of said plurality of digital adder circuits interspersed therebetween in the addition row with the carry propagation lines of the interspersed digital adder circuits coupled together and to the carry propagation lines of the predetermined ones of said digital adder circuits to form a high speed carry propagation line, and said regeneration means inverting the carry bits twice between the interspersed predetermined numbers of said plurality of digital adder circuits.