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US 4,368,523 AGranted
Liquid crystal display device having redundant pairs of address buses
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorKeiichi Kawate
Life of this patent
Estimating the term…
Abstract
Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix. The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.
Claims43
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) bridge means formed in said paired address buses for connecting one with the other of said paired address buses.
2 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to ssaid memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) bridge means formed in said paired data buses for connecting one with the other of said paired data buses.
2 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) bridge means formed in said paired address buses and in said paired data buses for connecting one with the other of said paired address buses and data buses.
2 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) electrode pads connected to at least one of both ends of said each address bus;
- and
- (e) bus driving means having output pads to be connected to said respective rows for driving said rows;
- wherein said electrode pad connected to said address bus at the non-defective side of said paired address buses of said respective rows is connected to the corresponding output pad of said bus driving means.
5 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to said memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- (d) electrode pads connected to at least one of both ends of said each data bus;
- and
- (e) bus driving means having output pads to be connected to said respective columns for driving said columns;
- wherein said electrode pad connected to said data bus at the non-defective side of said paired data buses of said respective columns is connected to the corresponding output pad of said bus driving means.
4 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- (d) address electrode pads connected to at least one of both ends of said each address bus;
- (e) data electrode pads connected to at least one of both ends of said each data bus;
- (f) address bus driving means having output pads connected to said respective rows for driving said rows;
- and
- (g) data bus driving means having output pads connected to said respective columns for driving said columns;
- wherein said address electrode pad connected to said address bus at the non-defective side of said paired address buses of said respective rows is connected to the corresponding output pad of said address bus driving means;
- and
- wherein said data electrode pad connected to said data bus at the non-defective side of said paired data buses of said respective columns is connected to the corresponding output pad of said data bus driving means.
8 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses connected to said memory cells and forming respective columns of said matrix;
- (d) fuse means disposed at two or more locations in a path of said each address bus for electrically interrupting said bus path as needed;
- and
- (e) means disposed between said address bus interposed between said fuse means at two locations and a predetermined potential part for preventing floating of said address bus.
3 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to said memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- (d) fuse means disposed at two or more locations in a path of said each data bus for electrically interrupting said bus path as needed;
- and
- (e) means disposed between said data bus interposed between said fuse means at two locations and a predetermined potential part for preventing floating of said data bus.
3 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) paired address buses connected to said memory cells and forming respective rows of said matrix;
- (c) paired data buses connected to said memory cells and forming respective columns of said matrix;
- (d) first fuse means disposed at two or more locations in a path of said each address bus for electrically interrupting said bus path as needed;
- (e) second fuse means disposed at two or more locations in a path of said each data bus for electrically interrupting said bus path as needed;
- and
- (f) means for preventing floating of said address bus and said data bus, disposed between said address bus interposed between said first fuse means at two locations and a predetermined potential part, and disposed between said data bus interposed between said second fuse means at two locations and a predetermined potential part.
4 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) paired address bus driver means connected to both ends of said address buses for driving said address buses, said paired driver means including paired driver blocks connected to both ends of said respective address buses, said paired blocks outputting same address signals to said address bus interposed between said bocks in synchronism with each other.
2 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses connected to said memory cells and forming respective columns of said matrix;
- and
- (d) paired data bus driver means connected to both ends of said data buses for driving said data buses, said paired driver means including paired driver blocks connected to both ends of said respective data buses, said paired blocks outputting same data signals to said data bus interposed betwen said blocks in synchronism with each other.
2 more elements
A memory device comprising:
- (a) a plurality of memory cells arranged in a matrix form;
- (b) address buses connected to said memory cells and forming respective rows of said matrix;
- (c) data buses conncted to said memory cells and forming respective columns of said matrix;
- (d) paired address bus driver means connected to both ends of said address buses for driving said address buses, said paired driver means including paired address bus driver blocks connected to both ends of said respective address buses, said paired blocks outputting same address signals to said address but interposed between said blocks in synchronism with each other;
- and
- (e) paired data bus driver means connected to both ends of said data buses for driving said data buses, said paired driver means including paired data bus driver blocks connected to both ends of said respective data buses, said paired blocks outputting same data signals to said data bus interposed between said blocks in synchronism with each other.
3 more elements
Dependencies are inferred from the claim text.