US 4,368,514 A · Multi-processor system

Abstract

There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave processor can access only its respective memory, the master processor can access either its own memory or any one of the slave memories. Maximum throughput (efficiency) is achieved by suspending operation of a single slave processor for only a single memory cycle, i.e., the time required for the master processor to access the respective slave memory. Each processor/memory is on a single card, with all of the cards being connected to a common bus. The cards are virtually identical, and master/slave distinctions are determined by a single slot bit on each card. A unique addressing scheme is implemented for access from the master to a selected slave.

Claims29

Dependent claims

A data processing system having a master processor and at least two slave processors;

a master memory and a plurality of slave memories, with each slave processor having access only to a respective slave memory and with the master processor having access both to the master memory and to all of the slave memories;
a common bus shared by all of said processors;
each processor having its own address/data bus connecting it to its respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor;
each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle;
and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and at any time to disable the access by any selected slave processor to its respective memory for no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

2 more elements

A data processing system having a master processor and at least two slave processors;

a master memory and a plurality of slave memories, with the master processor having access both to the master memory and to at least two of the slave memories;
a common bus;
each processor having its own address/data bus connecting it to a respective memory, and said master processor and the at least two slave processors associated with said at least two slave memories having means connected to said common bus for controlling said master processor to transmit address and data signals to said at least two slave memories and for controlling said at least two slave memories to transmit data signals to said master processor;
each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle;
and control means in said master processor and in each of said at least two slave processors, connected over said common bus, for disabling at any time the access by any selected one of said at least two slave processors to its respective memory while said master processor accesses such respective slave memory for no longer than the single processor cycle during which such master processor access takes place and said selected slave processor would otherwise access such respective slave memory.

2 more elements

A data processing system having a master processor and at least two slave processors;

a master memory and a plurality of slave memories, with the master processor having access to the master memory and priority access to all of the slave memories;
a common bus shared by all of said processors;
each processor having its own address/data bus connecting it to a respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor;
each of said processors including means for generating phase clock signals to enable an access to its respective memory during a respective processor cycle;
and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to inhibit at any time the access by any selected slave processor to its respective memory during no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

2 more elements

A data processing system having a master processor and at least two slave processors;

a master memory and a plurality of slave memories, with each slave processor having access to a respective slave memory and with the master processor having access to both the master memory and to all of the slave memories;
a common bus shared by all of said processors;
each processor having its own address/data bus connecting it to its respective memory, and said master processor and said slave processors having means connected to said common bus for controlling said master processor to transmit address and data signals to said slave memories and for controlling said slave memories to transmit data signals to said master processor;
each of said processors including clock-generating means for generating two phase clock signals to enable an access to its respective memory during a respective processor cycle, the processor outputting address signals during the first of said phase clock signals and a memory operation then taking place during the second of said phase clock signals;
and control means in said master processor and in each of said slave processors, connected over said common bus, for causing said master processor to synchronize the phase clock signals in each of said slave processors, and to disable at any time the access by any selected slave processor to its respective memory for no longer than the single processor cycle during which said master processor accesses such respective slave memory and said selected slave processor would otherwise access such respective slave memory.

2 more elements

A data processing system having a master processor, a first memory and at least two second memories;

with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space;
address and data buses connected between said master processor and all of said memories;
register means, settable by said master processor, for selectively identifying a particular one of said second memories;
means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register means;
whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required;
said register means being set by said master processor specifying an address which is in neither of said first and second address spaces, with said register means being set to identify a particular one of said second memories in accordance with data appearing on said data bus;
and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

4 more elements

A data processing system having a master processor, a first memory and at least two second memories;

with said first memory being accessed by said master processor specifying an address in a first address space and said at least two second memories being accessed by said master processor specifying an address in a second, different, address space;
address and data buses connected between said master processor and all of said memories;
register means, settable by said master processor, for selectively identifying a particular one of said second memories;
means connected to said first memory and said at least two second memories and said address and data buses, responsive to said master processor specifying an address in said second address space for accessing the particular one of said second memories identified by said register menas;
whereby, following setting of said register means by said master processor, said master processor can access said first memory or the identified particular second memory by specifying a respective address in said first or second address space without requiring a subsequent setting of said register means until such time that access by said master processor to another of said second memories is required;
and a plurality of additional processors each for accessing a respective one of said second memories by specifying an address in said second address space.

3 more elements

Dependencies are inferred from the claim text.

Multi-processor system

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Multi-processor system

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Abstract

Claims29