Memory device with fast word-line-discharging-circuits

#This invention relates to a memory, and more particularly, to a bipolar memory.

#In prior-art bipolar memories, each word line is constructed of a pair of word lines which consist of an upper word line and a lower word line, and memory cells are arranged at the points of intersection between each pair of word lines and pairs of data lines. The selection of the memory cell is executed by changing the voltage of the upper word line from a non-selection voltage to a selection voltage. In such a memory, in order to obtain a high speed for the memory selecting operation, it is necessary that after the word line is switched from select to non-select condition the word line voltage is changed at high speed from the selection voltage to the non-selection voltage.

#FIG. 1 is a schematic circuit diagram of a memory which has previously been proposed to this end by the assignee of the present application in Japanese Published Unexamined patent application No. 53-41968 and in U.S. Pat. No. 4,156,941, which is herein incorporated by reference.

#FIG. 1 is a circuit diagram of a prior-art bipolar memory;

#FIGS. 2(a) and 2(b) are time charts of signals for explaining the operation of the circuit in FIG. 1;

#FIGS. 3(a), 3(b) and 3(c) are diagrams illustrative of the changes of word line voltages for explaining a problem of the circuit in FIG. 1;

#An embodiment of this invention shown in FIG. 4, wherein like numerals designate like elements to FIG. 1, differs from the circuit of FIG. 1 in the point that a diode D.sub.0 which has a voltage source V.sub.CL connected to its cathode is connected to the base of the transistor Q.sub.203, and the point that the value of a resistance R.sub.204 ' is selected to be smaller than the value of the resistance R.sub.204 in the circuit of FIG. 1. The diode D.sub.0 serves to clamp the base voltage of the transistor Q.sub.203 to the supply voltage V.sub.CL.

#By way of example, as shown in FIG. 5(a), let it be supposed that in a case where the upper word line L.sub.X0 is selected, the voltage of the word line L.sub.X0 begins to rise from the non-selection voltage towards the selection voltage at a time t.sub.1 until it reaches the selection voltage at a time t.sub.2. This voltage then falls over from a time t.sub.3 to a time t.sub.4. The supply of the voltage to the word line L.sub.X0 is executed by a known driver (not shown). The driver delivers the voltage pulse switching from the non-selection voltage to the selection voltage as stated above, to the upper word line to-be-selected in response to an address signal.

#The emitter-follower transistor Q.sub.201 detects this change of the voltage of the word line, and its emitter voltage changes with the same waveform as the waveform of FIG. 5(a). This voltage change produces a voltage change as shown in FIG. 5(b) in the base of the transistor Q.sub.203 under the action of the resistance R.sub.201 as well as the constant-current circuit which is composed of the transistor Q.sub.202, the resistance R.sub.202 and the voltage source V.sub.EE. When the voltage of the word line L.sub.X0 rises from the non-selection voltage towards the selection voltage, the base voltage of the transistor Q.sub.203 also rises.