Circuit arrangement for the recognition of predetermined binary valves of a specific minimum duration

In a data transmission system of the type in which a plurality of data sources emit data to a common data line via respective switches, the improvement therein comprising:

• a circuit arrangement for recognizing predetermined binary values of a specific minimum duration, said circuit arrangement including
• an address decoder for receiving and decoding addresses and responsive thereto to selectively operate the switches,
• an address generator connected to said address decoder and operable to periodically generate addresses identifying the data sources, and
• counting means connected to said address generator, said counting means operable to assign a counter reading to each of said data sources and including a forward-backward counter connected to the data line and operable to count in a respective direction in response to the presence or absence of the predetermined binary values and produce recognition signals in response to reaching predetermined counter readings.