Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film;
• a gate circuit including a MOS transistor serially connected to said memory cell;
• a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit;
• an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit;
• a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit;
• and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V.sub.G -V.sub.TH >V.sub.D for each of said MOS transistors, wherein V.sub.G designates the gate voltage, V.sub.TH designates the threshold voltage and V.sub.D designates the drain voltage;
• the conductivity type of said MOS transistors included in said writing selection circuit being different from the conductivity type of said MOS transistor forming said memory element.

A semiconductor memory device comprising:

• a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film;
• a gate circuit including a MOS transistor serially connected to said memory cell;
• a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit;
• an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit;
• a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit;
• and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit;
• said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V.sub.G -V.sub.TH >V.sub.D for each of said MOS transistors, wherein V.sub.G designates the gate voltage, V.sub.TH designates the threshold voltage and V.sub.D designates the drain voltage;
• the conductivity type of said MOS transistors included in said readout selection circuit being different from the conductivity type of said MOS transistor forming said memory element.

A semiconductor memory device comprising:

• a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film;
• a gate circuit including a MOS transistor serially connected to said memory cell;
• a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit;
• an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit;
• a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit;
• and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V.sub.G -V.sub.TH >V.sub.D for each of said MOS transistors, wherein V.sub.G designates the gate voltage, V.sub.TH designates the threshold voltage and V.sub.D designates the drain voltage;
• the conductivity type of said MOS transistors included in said output buffer circuit being different from the conductivity type of said MOS transistor forming said memory element.