Adder for exponent arithmetic

For use in a data processing system having an arithmetic system for performing floating-point arithmetic calculations in two data formats wherein each format includes a characteristic portion representing an exponent and a mantissa portion representing data, unpacking circuitry for separating the characteristics and the mantissas and positioning the characteristics depending upon the data format, a main adder for adding or subtracting the mantissas, a shifting matrix for shifting selected ones of the mantissas for alignment prior to addition or subtraction according to a calculated shift count determined from the relationship of the characteristics, registers for storing the characteristics, normalizing circuitry for normalizing the results, and control circuitry for controlling sequences of each floating-point instruction pursuant to an instruction word, circuitry for biasing and combining the resultant mantissa and resultant characteristic, a characteristic adder comprising:

• first operand input means for receiving a first operand from the register storing it;
• second operand input means for receiving a second operand from the register storing it;
• exclusive-OR means coupled to said second operand input means for selectively providing the true or 1's complement value of said second operand;
• adder means including
• first half-add means coupled to said first operand input means and said exclusive-OR means for generating borrow and propagate signals derived from said first and second operands;
• borrow look ahead means coupled to said first half-add means for providing group borrow signals and group propagate signals;
• second half-add means partitioned in predetermined bit groupings and including ripple borrow means within said bit groupings and coupled to said first half-add means and said borrow look ahead means for forming said sum;
• output signaling means for providing output signals when said second operand is numerically greater than said first operand for controlling which mantissa will be selected for shifting in alignment;
• first and second overflow detecting means for selectively providing first and second overflow indicating signals indicative of overflow error conditions;
• negative result detecting means for providing adder output negative signals when said sum is negative;
• function input means for receiving function signals indicative of selected operations of said adder means;
• function control means coupled to said function input means, said negative result detecting means and said overflow detecting means and said adder means for selectively controlling operation of said adder means in response to said function signals;
• magnitude means for selectively providing the magnitude output of said sum;
• complement means for selectively providing the 1's complement of said sum;
• format means coupled to said adder means and said function control means for selectively converting said sum to a first data word format in response to first format selection signals and to a second data format in response to second format signals;
• underflow means coupled to said overflow means, said negative result detecting means and said function control means for selectively providing underflow indicating signals indicative of an underflow error condition;
• overflow and underflow disabling means for selectively inhibiting generation of said overflow indicating signals and said underflow indicating signals;
• magnitude detection means coupled to said adder means and said function control means for selectively detecting when said sum exceeds a predetermined threshold value.