Cycle control for a microprocessor with multi-speed control stores

Abstract

A system for controlling the cycle time of a central processing unit having associated control store memory units for the storage of information is provided. The system includes a plurality of control store memory locations disposed within the control store memory units for the storage of information. A plurality of control store memory locations are operable at varying speeds and are accessible by the central processing unit. Circuitry is provided for addressing one of the plurality of control store memory locations responsive to address information contained within the information stored within the plurality of control store memory locations. The addressed information selects the next successive control store memory location to be addressed by a central processing unit. The system further includes logic circuitry for dynamically controlling the cycle time of the central processing unit in response to the addressed information and the speed of the location of the next successive one of the plurality of control store memory locations to be accessed by the central processing unit where the cycle time of the central processing unit automatically adjusts to the speed of the next successive addressed control store memory location.

Dependencies are inferred from the claim text.