Memory controller with burst mode capability

A memory controller for use in a system including at least one request generating unit coupled to a bus in common with said controller, said controller being coupled to a plurality of memory modules including a plurality of word locations in each module and said controller being operative to control the operation of said modues in response to memory requests generated by said unit, said memory requests including predetermined types of memory requests coded to specify the read out of predetermined numbers of data words over successive memory cycles of operation and each predetermined type of memory request including a memory address specifying where in said memory modules the read out of said words is to begin, said controller comprising:

• a plurality of address counter circuits corresponding in number to said plurality of memory modules, each address counter control circuit being coupled to said bus for receiving a predetermined address portion of each said memory request address and each address counter circuit being operatively coupled to apply address signals to said number of modules for specifying the pair of locations to be addressed during each of said successive memory cycles of operation;
• and,
• mode control means coupled to said plurality of address counter circuits and to said bus, said mode control means being operative in response to each predetermined type of request to load said predetermined address portion into an available one of said plurality of address counter circuits and for switching from a first state to a second state, placing said controller in a predetermined mode of operation, said mode control means when in said second state generating signals for incrementing by one said predetermined address portion, the contents of one of said plurality of said address counter circuits after each memory cycle of operation of said predetermined type of request, enabling the read out of successive pairs of words from consecutive pairs of locations in said number of memory modules to said bus, and said one address counter circuit upon being incremented to a predetermined count, generating an output signal indicating the read out of a last word pair, said mode control means switching from said second state to said first state in response to said output signal indicative of the availability of said one address counter circuit and the readiness of said controller to accept another predetermined type of memory request.

A memory controller for use in a system including a data processing unit and a high speed storage unit coupled to a bus in common with said controller, said controller being coupled to a plurality of memory modules, each including a plurality of word locations, and said controller being operative to control the operation of said modules in response to memory requests generated by said units, said memory requests including burst memory requests coded to specify the read out of predetermined numbers of data words over successive memory cycles of operation and each burst memory request including a memory address specifying where in said memory modules the read out of a pair of words is to begin, said controller comprising:

• a plurality of address counter circuits each being individually coupled to said bus for receiving predetermined portions of said memory request addresses and said each address counter circuit being operatively coupled to apply address signals to said plurality of modules for specifying pairs of locations to be addressed during each of said successive memory cycles of operation;
• and,
• a plurality of mode control means coupled to a different one of said address counter circuits and to said bus, each of said plurality of mode control means when selected as available to process one of said burst requests, being operative in response to said burst request to switch from a first state to a second state, conditioning said controller for operating in a burst mode of operation, each of said mode control means when in said second state generating signals for incrementing by one said predetermined address portion, the contents of said different one of said plurality of address counter circuits after each consecutive memory cycle of operation of said burst request enabling the read out of successive pairs of words from consecutive locations of said memory modules, and said different one of said plurality of address counter circuits upon being incremented to a predetermined count, generating an output signal indicating the termination of said burst mode operation, said each mode control means switching from said second state to said first state indicative of the availability of said different one of said plurality of address counter circuits for processing another burst memory request.