Memory controller with queue control apparatus
AssigneeHoneywell Information Systems Inc.
InventorsRobert B. Johnson, Chester M. Nibby, Jr.
Life of this patent
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Abstract
A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.
Claims26
A memory controller for use in a system including at least one request generating unit coupled to a bus in common with said controller, said controller being coupled to at least one memory module for controlling the operation of said module in response to a number of different types of memory requests generated by said unit requiring one or more memory cycles of operation, said module including a plurality of word locations and said controller including control circuits for generating command signals requesting said controller to perform internal operations requiring memory cycles of operation, said controller comprising:
- at least a pair of queue circuit means, each being coupled in common to said module and to said bus, for receiving a different one of said plurality of memory requests;
- queue control means coupled to each of said pair of queue circuit means and to said control circuits;
- and,
- memory cycle control means coupled to said queue control means, to said control circuits and to said bus for receiving said command signals, signals from said queue control means indicative of the status of said pair of queue circuit means in processing said requests and signals from said bus indicating the receipt of a request from said unit, said memory cycle control means being operative in response to said signals to generate signals for producing succeeding memory cycles of operation as required for the processing of internal operations and said memory requests so as to minimize conflict therebetween.
A memory controller for use in a system including at least one request generating unit coupled to a bus in common with said controller, said controller being coupled to a number of memory modules for controlling the operation of said module in response to a number of different types of memory requests generated by said unit requiring memory cycles of operation, each of said modules including a plurality of word locations and said controller including refresh control circuits for periodically generating refresh command signals requesting said controller to perform refresh operations upon said plurality of word locations of said number of memory modules, said controller comprising:
- at least a pair of queue circuit means, each being coupled in common to said number of memory modules and to said bus, for receiving a different one of said plurality of memory requests;
- queue control means coupled to each of said pair of queue circuit means and to said refresh control circuits, said queue control means including cycle control means for indicating when one of said pair of queue circuit means has completed a memory cycle of operation;
- and,
- memory cycle control means coupled to said queue control means, to said refresh control circuit and to said bus for receiving said refresh command signals, signals from said queue control means indicative of the status of said pair of queue circuit means and signals from said bus indicating the receipt of a request from said unit and said signals from said cycle control means, said memory cycle control means being operative to generate signals for producing succeeding memory cycles of operation as required for the processing of refresh operations and for processing memory requests received concurrently so as to minimize conflict.
A memory controller for use in a system including a plurality of request generating units coupled to a bus in common with said controller, said controller being coupled to a pair of memory modules for controlling the operation of said modules in response to a number of different types of memory requests generated by said units, said requests including predetermined types of requests requiring a plurality of memory cycles of operation, each of said modules including a plurality of word locations and said controller including refresh control circuits for periodically generating refresh command signals requesting said controller to perform refresh operations upon said plurality of word locations within each of said modules, said controller comprising:
- a pair of queue circuits, each queue circuit being coupled in common to said plurality of said modules and to said bus, for receiving a different one of said plurality of memory requests;
- queue control means coupled to each of said pair of queue circuits and to said refresh control circuits, said queue control means including cycle control means for indicating when one of said pair of queue circuits has completed a memory cycle of operation;
- and,
- memory cycle control means coupled to said queue control means, to said refresh control circuits and to said bus for receiving said refresh command signals, signals from said queue control means indicative of the status of said pair of queue circuit means and signals from said bus indicating the receipt of a request from one of said units and said signals from said cycle control means, said memory cycle control means being operative to generate signals for producing succeeding memory cycles of operation as required for the processing of refresh operations with memory requests concurrently received from said units so as to minimize conflict.
Dependencies are inferred from the claim text.