Self-snubbing bipolar/field effect (biofet) switching circuits and method

A method of snubbing a first semiconductor switching device with a second semiconductor switching device, said first and second switching devices each having a main current path, and a control electrode for receiving first and second control signals, respectively, the control electrodes of said first and second switching devices being responsive to first levels of said first and second control signals, respectively, so the first and second switching devices are turned on to substantially reduce the relative impedances of their respective main current paths, the control electrodes of said first and second switching devices being respectively responsive to second levels of the first and second control signals so the first and second switching devices are turned off to increase the relative impedances of their respective main current paths, said first switching device being characterized by having a substantially lower impedance in its main current path when turned on relative to said second switching device when turned on, said first switching device being further characterized by susceptibility to damage due to peak power dissipation therein caused by the application of high-operating voltage across the main current path, concurrent with high current therethrough, during the time intervals for turning on and turning off this device, said second switching device being further characterized by the capability to withstand substantially higher peak power dissipation relative to said first switching device in switching from one of its turned-on or turned-off conditions to the other, the main current path of said second switching device being connected across the main current path of said first switching device, comprising the steps of:

• turning on said second switching device by applying the first level of the second signal to the central electrode of the second device concurrent with said first switching device being turned off in response to the second level of the first signal being applied to the control electrode of the first device, for substantially reducing the voltage level across the main current path of the latter to the voltage level across the main current path of the former;
• then, turning on said first switching device by applying the first level of the first signal to the control electrode of the first device while maintaining the said second switching device turned on by applying the first level of the second signal to the control electrode of the second device, the latter providing turn-on snubbing for the former;
• and
• then, turning off said first switching device by applying the second level of the first signal to the control electrode of the first device, while maintaining said second switching device turned on by applying the first level of the second signal to the control electrode of the second device, the latter providing turn-off snubbing for the former.

A transistorized switching circuit operable for switching high-magnitudes of current at high-levels of voltage, comprises:

• a first terminal for receiving a source of operating voltage;
• a second terminal for receiving a source of reference voltage;
• bipolar switching transistor means having a collector electrode connected to said first terminal, an emitter electrode connected to said second terminal, and a base electrode;
• solid-state switching means having main current paths connected between said first and second terminals, first and second input terminals for receiving first and second control signals, respectively, and an output terminal connected to said base electrode, said solid-state switching means being responsive to said first and second control signals applied to the first and second input terminals sequentially operable to a first condition for preventing the flow of base current in said bipolar switching transistor means, thereby keeping the latter turned off with the voltage at said collector having a level substantially equal to that of said operating voltage, to a second condition for substantially reducing the level of voltage between said collector and emitter electrodes, while preventing the flow of base current in said bipolar switching transistor means, and to a third condition for permitting the flow of current between said first terminal and said base electrode of said bipolar switching transistor means, the current flow between the first terminal and said base electrode turning on the latter bipolar transistor to substantially reduce the level of impedance between the collector and emitter and permit load current to flow therebetween, said solid-state switching means being sequentially operable from its third, to its second, to its first conditions, for turning off said bipolar switching transistor means, whereby said solid-state switching means permits said bipolar switching transistor means to be turned on and off at times that the level of voltage at its collector electrode is substantially low relative to said operating voltage, thereby providing snubbing of said bipolar switching transistor means, for high-speed switching of high magnitudes of current at high levels of voltage.

A method for operating a bipolar power transistor having base, collector, and emitter electrodes, for receiving a control current, an operating voltage, and a source of reference voltage, respectively, to switch high magnitudes of current at high-voltage levels, while providing active snubbing during turn-on and turn-off of the bipolar transistor, comprising the steps of:

• (1) preventing the flow of base current in said bipolar power transistor for maintaining said transistor turned off by connecting a relatively high impedance between said collector and base electrodes;
• and connecting a relatively low value of impedance between said base and emitter electrodes;
• (2) reducing substantially the level of voltage across said collector and emitter electrodes relative to the level of said operating voltage, for initiating a turn-on cycle;
• (3) supplying current to the base electrode of said bipolar transistor for completing its turn-on cycle;
• (4) removing the supply of base current from said base electrode, concurrent with limiting the rise of the level of the voltage at said collector electrode to that of step (2), for initiating the turn-off cycle for said bipolar transistor;
• and
• (5) permitting the level of voltage at said collector electrode to substantially approach the level of said operating voltage, for completing the turn-off cycle.

A transistorized switching device, comprising:

• a bipolar transistor having a collector electrode for receiving an operating voltage, an emitter electrode for connection to a source of reference potential, and a base electrode for receiving a first control signal;
• and
• a field-effect transistor having drain and source electrodes connected to said collector and emitter electrodes, respectively, and a gate electrode for receiving a second control signal;
• said transistorized switching device being operable for turning on said field-effect transistor before said bipolar transistor for substantially reducing the voltage across the collector and emitter electrodes of the latter, which is then turned on and off as desired at substantially reduced peak power dissipation via the snubbing effect of the field-effect transistor.

A transistorized switching device operable for switching high-magnitudes of current at high levels of voltage, comprises:

• a first terminal for receiving an operating voltage;
• a second terminal for connection to a source of reference potential;
• a third terminal for receiving a first control signal;
• a fourth terminal for receiving a second control signal;
• bipolar switching transistor means having a collector electrode connected to said first terminal, an emitter electrode connected to said second terminal, and a base electrode;
• a first field-effect transistor having a channel connected between said collector and base electrodes, and a gate electrode connected to said third terminal;
• and
• a second field-effect transistor having a channel connected between said base and emitter electrodes, and a gate electrode connected to said fourth terminal, whereby said first and second field-effect transistors each have substantially high channel impedance when turned off, and relatively low channel impedance when turned on;
• said transistorized switching device being operable in response to different combinations of levels of said first and second control signals, to a first condition having said first field-effect transistor turned off concurrent with said second field-effect transistor turned on, for maintaining said bipolar switching transistor means turned off, to a second condition having said first and second field-effect switching transistors concurrently turned on, thereby substantially lowering the level of voltage across said collector and emitter electrodes relative to said operating voltage, while preventing the flow of base current in said bipolar switching transistor means, maintaining the latter turned off, and to a third condition having said first field-effect switching transistor turned on, concurrent with said second field effect transistor being turned off for permitting base current to flow in said bipolar switching transistor means, turning on the latter, said transistorized switching device being turned on via sequential operation through its first through third conditions, and being turned off via sequential operation in the reverse order from turn-on, whereby said second condition provides both turn-on and turn-off snubbing of said bi-polar switching transistor means.

A transistorized switching device operable for switching high magnitudes of current at high levels of voltage, comprises:

• a first terminal for receiving an operating voltage;
• a second terminal for receiving reference potential;
• a third terminal for receiving a first control signal;
• a fourth terminal for receiving a second control signal;
• bipolar switching transistor means having a collector electrode terminal connected to a first terminal, an emitter electrode connected to said first terminal, and a base electrode;
• a first field-effect transistor having a channel connected between said collector and emitter electrodes, and a gate electrode connected to said third terminal;
• and
• a second field-effect transistor having a channel connected between said collector and base electrodes, and a gate electrode connected to said fourth terminal, said first and second field-effect transistors having substantially high channel impedances, when turned off, and substantially low channel impedances when turned on;
• said transistorized switching device being operable, in response to different combinations of levels of said first and second control signals, to a first condition, whereby said first and second field-effect transistors are turned off for maintaining said bipolar transistor means turned off, to a second condition whereby said first field-effect transistor is turned on, concurrent with said second field-effect transistor being turned off, thereby establishing a substantially low level of voltage across said collector and emitter electrodes relative to level of said operating voltage, with said bipolar switching transistor means being turned off, and to a third condition whereby said first and second field effect transistors are concurrently turned on, the turn-on of said second field-effect transistor permitting base current to flow in said bipolar transistor and, turning on the latter at a time that the voltage at its collector electrode is substantially lower than that of said operating voltage due to said first field-effect transistor being turned on, said transistorized switching device being turned on via the sequential operation of this device through its first through third conditions, and being turned off via sequential operation in the reverse order from turn-on, whereby said second condition provides both turn-on and turn-off snubbing of said bipolar switching transistor means.

An active device for "snubbing" the main current path of a power semiconductor switch, comprising:

• first and second terminals for connection to different ends of the main current path of said power semiconductor switch, respectively;
• a third terminal for receiving a control signal;
• and
• transistorized switching means having a main current path connected between said first and second terminals, and a control electrode connected to said third terminal, said transistorized switching means being operable in response to different levels of said control signal, to a turned-on condition in which its main current path has a relatively low impedance, and to a turned-off condition in which its main current path has a relatively high impedance, said transistorized switching device being characterized by the capability to withstand higher peak power than said power semiconductor switch, the main current path of said transistorized switching device also having a substantially higher impedance relative to the main current path of said power semiconductor switch when each is in its turned-on condition, said transistorized switching means being turned on at least prior to the times of turning on or turning off said power semiconductor switch, said transistorized switching means consists of a relatively high power field-effect transistor having drain and source electrodes connected to said first and second terminals, respectively, and a gate electrode connected to said third terminal.

In combination, a pair of d.c. power supply terminals, a load, a power transistor having a control electrode and a main conducting path, the main conducting path, load and pair of d.c. power supply terminals being connected in series with each other, the impedance of the main conducting path being relatively high and low in response to first and second signal levels respectively applied to the control electrode, semiconductor means having control terminal means and first and second terminals shunting the main conducting path and connected in series with the load, the impedance of the semiconductor means between the first and second terminals being relatively high and low in response to low and high signal amplitudes respectively applied to the control terminal means, the low impedance between the first and second terminals being substantially higher than the low impedance of the main conducting path but much lower than the high impedances, the power consumption of the power transistor while in the low impedance state being much less than the power consumption of the semiconductor means in the low impedance state, the power transistor having a tendency to be damaged in response to the full load voltage and current at the time of transitions between the high and low impedance states of the main conducting path, a first signal source having transitions between the first and second signal levels connected to the control electrode, second signal source means having transitions between the high and low signal amplitudes connected to the control terminal means, the transitions of the first signal source between the first and second levels activating the power transistor between the high and low impedance states thereof occurring while the impedance between the first and second terminals is low in response to the second signal source means maintaining the control terminal means at the high signal amplitude.

In combination, a pair of d.c. power supply terminals, a load, a power transistor having a control electrode and a main conducting path, the main conducting path, load and pair of d.c. power supply terminals being connected in series with each other, the impedance of the main conducting path being relatively high and low in response to first and second signal levels respectively applied to the control electrode, semiconductor means having control terminal means and first and second terminals shunting the main conducting path and connected in series with the load, the impedance of the semiconductor means between the first and second terminals being relatively high and low in response to low and high signal amplitudes respectively applied to the control terminal means, the low impedance between the first and second terminals being substantially higher than the low impedance of the main conducting path but much lower than the high impedances, the power consumption of the power transistor while in the low impedance state being much less than the power consumption of the semiconductor means in the low impedance state, the power transistor having a tendency to be damaged in response to the full load voltage and current at the time of transitions between the high and low impedance states of the main conducting path, a first signal source having transitions between the first and second signal levels connected to the control electrode, second signal source means having transitions between the high and low signal amplitudes connected to the control terminal means, the transitions of the first signal source between the first and second levels activating the power transistor between the high and low impedance states thereof occurring while the impedance between the first and second terminals is low in response to the second signal source means maintaining the control terminal means at the high signal amplitude, the transitions of the second signal source occurring while no transitions of the main path impedance are occurring.