PCM Decoder

A PCM decoder comprising

• a first circuit for receiving in series input PCM signals forming signalling frames and non-signalling frames and for outputting in parallel the PCM signals;
• a second circuit for delivering first and second control signals in accordance with the contents of said parallel output PCM signals;
• a third circuit including first to eighth binary-weighted capacitors each having two ends, one end being connected with an output line and the other end connected selectively with one of plural voltage supply lines through a corresponding one of a first plurality of switches controlled by said first control signals;
• and
• a fourth circuit having a voltage source and a resistor string circuit which is provided with plural intermediate taps for taking out divided portions of a voltage of said voltage source so that the voltage at one of said intermediate taps may be applied to one of said voltage supply lines through one of a second plurality of switches controlled by said second control signals;
• an analog voltage corresponding to said PCM signal being delivered onto the output line of said third circuit, wherein said resistor string circuit has a first group of intermediate taps from which a decoding voltage for said parallel PCM signals corresponding to the non-signalling frames is derived and a second group of intermediate taps from which a decoding voltage for said parallel PCM signals corresponding to the signalling frames is derived and wherein said second circuit receives signalling frame signals and also delivers said second control signals to select one of said intermediate taps of said first and second groups in accordance with the content of said signalling frame signals.