Delay gate circuit
AssigneeBell Telephone Laboratories, Incorporated
InventorHoward C. Kirsch
Life of this patent
Estimating the term…
Abstract
A delay gate circuit consists of first and second stages which each have two serially connected MOS transistors and of a fifth MOS transistor. The gates of the transistors of the first stage serve as first and second circuit input terminals. The gate of the second transistor of the first stage is connected to the gate of the first transistor of the second stage. An output terminal of the first stage is connected to the gate of the second transistor of the second stage and to the drain of the fifth MOS transistor. An output terminal of the second stage is connected to the gate of the fifth transistor and serves as the output circuit terminal.
Claims2
Circuitry comprising:
- first, second, third, and fourth switching devices (Q10, Q11, Q12, and Q13, respectively) each having a control terminal and first and second output terminals;
- the second output terminal of the first switching device (Q10) being coupled to the first output terminal of the second switching device (Q11), to the control terminal of the fourth switching device (Q13), and to a first circuitry terminal (30);
- the control terminals of the second and third switching devices (Q11 and Q12) being coupled together to a second circuitry terminal (22);
- the second output terminal of the third switching device (Q12) being coupled to the first output terminal of the fourth switching device (Q13) and to a third circuitry terminal 20;
- the control terminal of the first switching device (Q10) serving as a first input terminal;
- the second circuitry terminal (22) serving as a second input terminal;
- the third circuitry terminal (20) serving as a circuitry output terminal;
- and
- the first output terminals of the first and third switching devices (Q10 and Q12) being coupled together and being connectable to a first biasing source (VDD);
- the second output terminals of the second and fourth (Q11 and Q13) switching devices being coupled together and being connectable to a second biasing source (VSS);
- and
- a fifth switching device (Q14) having a control terminal coupled to the third circuitry terminal (20), said fifth switching device having a first output terminal coupled to the first circuitry terminal (30) and having a second output terminal coupled to the second output terminal of the second switching device (Q11).
Dependencies are inferred from the claim text.