Amplifier circuit
AssigneeFujitsu Limited
InventorFumitaka Asami
Life of this patent
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Abstract
An amplifier circuit composed of two cascade-connected inverter stages, each of which consists of p channel and n channel transistors connected at their drains, n channel and p channel transistors which connect the gates of the, transistors of the first inverter to their respective drains by means of the control signal while said amplifier circuit is operated, and n channel and p channel transistors which connect the gates of both transistors of the first inverter respectively to specified potentials which set both transistors at the cut-off condition by means of the control signal while said amplifier circuit is not operated.
Claims10
An improved amplifier circuit of the type including a cascade connection of first and second inverters, each of which consists of series connected p channel and n channel transistors, with the amplifier having an input port connected to the input of the first inverter for receiving a signal to be amplified and having an output port connected to the output of the second inverter for delivering an amplified signal, wherein the improvement comprises:
- first means for connecting the gates of both transistors of said first inverter to their respective drains when said amplifier is being operated;
- second means for connecting said gates of both transistors of said first inverter to potentials which set said both transistors of said first inverter at their cut-off conditions when said amplifier is not operated;
- and control port means for receiving a control signal for controlling the first and second means.
An amplifier circuit having an input port for receiving a signal to be amplified, an output port for delivering the amplified signal to subsequent circuitry, and a control port for receiving a control signal to selectively render the amplifier operative and inoperative, comprising:
- means for receiving power from a power supply;
- a first p channel transistor and a first n channel transistor series-connected, at a first intermediate connection point, between said means for receiving power and ground;
- an input element and means for conveying a feedback signal series-connected, at a second intermediate connection point, between said input port and said first intermediate connection point;
- a second p channel transistor and a second n channel transistor series-connected, at a third intermediate connection point, between said means for receiving power and said second intermediate connection point, the gate of one of said first transistors being connected to said third intermediate connection point and the gates of both second transistors being connected to said control port;
- a third p channel transistor and a third n channel transistor series connected, at a fourth intermediate connection point, between said means for receiving power and ground, the gates of both third transistors being connected to said control port;
- a fourth p channel transistor and a fourth n channel transistor series connected, at a fifth intermediate connection point, between said second intermediate connection point and ground, the gate of the other of said first transistors being connected to said fifth intermediate connection point and the gates of both fourth transistors being connected to said fourth intermediate connection point;
- and
- means connected to said first intermediate connection point for providing an output signal at said output port.
Dependencies are inferred from the claim text.