Level conversion circuit

#This invention relates to a level conversion circuit such as one used as the interface between the output of an ECL circuit and the input of a TTL circuit or an N-MOS circuit, for example.

#Since the ECL (emitter coupled logic) circuit makes use of a negative power source voltage V.sub.EE, the signal level of the ECL circuit varies between ground potential (GND) and the negative power source voltage V.sub.EE. On the other hand, the TTL (transistor-transistor logic) circuit or the N-MOS (N channel insulated gate field effect transistor) circuit makes use of a positive power source voltage V.sub.CC and hence, the signal level of the TTL circuit or of the N-MOS circuit varies between the positive power source voltage V.sub.CC and ground potential (GND).

#As the interface between the output of the first circuit operating on the negative power source voltage V.sub.EE and the input of the second circuit operating on the positive power source voltage V.sub.CC, a signal level conversion circuit is necessary. In an IC.sub.1 encompassed by the two-dot chain line in FIG. 1, a circuit indicated by l.sub.2 is a heretofore known semiconductor integrated circuit, forming a signal level conversion circuit. A first power terminal of the ECL circuit l.sub.1 is connected to the ground potential (GND) and a negative power source voltage V.sub.EE (e.g., -5.2 V) is impressed upon a second power terminal P.sub.2. Accordingly, the signal level of an output signal y obtained from an output terminal P.sub.7 of the ECL circuit l.sub.1 varies between the ground potential (GND) and the negative power source voltage V.sub.EE. A positive power source voltage V.sub.CC (e.g., +5.0 V) is impressed upon a first power terminal P.sub.10 of the TTL circuit l.sub.3 and its second power terminal P.sub.16 is connected to the ground potential (GND). Hence, the signal level of the TTL circuit l.sub.3 varies between the positive power source voltage V.sub.CC and ground potential (GND). The heretofore known level conversion circuit l.sub.2 is disposed between the output terminal P.sub.7 of the ECL circuit l.sub.1 and the input terminal P.sub.15 of the TTL circuit l.sub.3.

#FIG. 1 is a circuit diagram of the heretofore known circuit;

#FIG. 2 is a circuit diagram of an embodiment of the present invention;

#FIG. 3 is a block diagram of a MOS memory;

#Hereinafter, the preferred embodiments of the present invention will be explained in detail.

#FIG. 2 is a circuit diagram showing the signal level conversion circuit l.sub.2 of an embodiment of the present invention together with the ECL circuit l.sub.1 and the N-MOS memory l.sub.3.

#Though not limited in particular, the abovementioned ECL circuit l.sub.1 comprises a bias circuit consisting of resistors R.sub.1 -R.sub.3, diodes D.sub.1 and D.sub.2 and a transistor Q.sub.1 and a logic circuit consisting of resistors R.sub.4 -R.sub.6 and transistors Q.sub.2 -Q.sub.7 as shown in the drawing.