US 4,366,393 A · Integrated logic circuit adapted to performance tests

Abstract

An easily testable integrated logic circuit utilizes a plurality of flip-flops to form a feedback shift register. In some embodiments, means are provided for selectively forming the flip-flops into a feedback shift register and for selectively supplying either the flip-flop contents or a random signal as partial inputs to the combinational logic circuit. In other embodiments, the feedback shift register is coupled to the AND logic array outputs of a combinational circuit which also includes an OR logic array.

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Drawings

Claims9

Dependent claims

An easily testable integrated logic circuit, comprising:

a logic circuit receiving a plurality of first inputs and a plurality of second inputs for providing logic outputs;
means for generating a random signal;
multiplexing means having first and second multiplexing inputs and which, in response to a control signal, selectively supplies said first multiplexing inputs as said second logic inputs, said first multiplexing inputs being received from said random number generator;
means for applying said control signal to said multiplexing means;
a plurality of flip-flops for receiving and storing outputs from said logic circuit, the outputs of said flip-flops being fed back to the second input of said multiplexing means;
and
means for coupling said flip-flops to form a feedback shift register in response to said control signal, the output of one of said flip-flops constituting the output of said feedback shift register.

4 more elements

An easily testable integrated logic circuit, comprising:

a combinational logic circuit including an AND logic array having a plurality of input terminals and having a plurality of output terminals on which are provided logical products of selected combinations of said input terminals, and an OR logic array for receiving as inputs the outputs from said AND logic array and having output terminals on which are provided logical sums of selected combinations of said AND logic array outputs;
an internal register having P stages for receiving P different outputs from said OR logic array, the contents of said internal register being provided as inputs to said AND logic array;
a feedback shift register comprising:
a first plurality of M flip-flops each having an input and an output, the output of one of said M flip-flops constituting an output of said feedback shift register;
a second plurality of P flip-flops each having an input and an output;
a feedback modulo-2 adder for receiving and combining selected outputs from said first and second pluralities of flip-flops;
a first plurality of P modulo-2 adders each having at least first and second inputs and an output, each of said P modulo-2 adders providing its output as an input to one of said P flip-flops and each receiving as its first input the contents from a respective stage of said internal shift register, (P-1) of said first plurality of modulo-2 adders receiving their second inputs from the outputs of respective ones of said P flip-flops, the remaining one of said P modulo-2 adders receiving its second input from the output of said feedback modulo-2 adder;
and
a second plurality of M modulo-2 adders each having at least first and second inputs and an output, each of said M modulo-2 adders providing its output as an input to one of said M flip-flops and each receiving as its first input a respective output from said AND logic array, (M-1) of said second plurality of modulo-2 adders receiving their second inputs from the outputs of respective ones of said M flip-flops, the remaining one of said M modulo-2 adders receiving its second input from the output of one of said P flip-flops.

6 more elements

Dependencies are inferred from the claim text.

Description4,981 words

Summary708 words

#The present invention relates to readily testable integrated logic circuits, and more particularly to general-purpose integrated logic circuits of systematic structure having built-in flipflops, whose structural elements can be readily tested for correct operation.

#While circuit integration technology has achieved remarkable progress over recent years, successfully realizing high-density integration of highly complex logic functions, detection of faulty elements has been made even more difficult by such constraints as circuit complexity, limitation on the number of input and output terminals and the impossibility of directly inspecting the internal structure. Programmable logic arrays (hereinafter abbreviated to PLAs) find increasingly extensive use as general-purpose integrated logic circuit elements because of their versatility and design facility. They so much the more require ready detection of faulty elements.

#However, testing a large integrated logic circuit with respect to all possible input combinations would take an enormous length of time. More recently, there have emerged PLAs which, having built-in flipflops, permit composition of sequential circuits capable of more complex logical operations, and their testing is even more difficult. These integrated logic circuits are, therefore, so designed in advance to allow ready examination of faulty elements whenever they arise.

Brief description of the drawings10 figures

#The above and other objects, features and advantages of this invention will be understood from the following detailed description of preferred embodiments of this invention taken in conjunction with the accompanying drawings, wherein:

#FIG. 1 is a block diagram of a first embodiment of this invention;

#FIG. 2 is a block diagram of the random signal generator 3 used in the first embodiment shown in FIG. 1;

Detailed description4,057 words

#Referring now to FIG. 1, the first embodiment 100 comprises a multi-input, multi-output combinational logic circuit 1, which can be of any structure appropriate for the logic functions to be realized, e.g. an AND logic array and OR logic array in a PLA. The logic circuit 1 logically combines an external input X and a feedback input Y' and supplies an external output Z and a flipflop-driving signal Y. A register 2 includes a group of flipflops corresponding to the internal memory elements of a sequential circuit, and is also used as a compressor for the signal sequence.

#The first embodiment 100 further comprises signal lines 101 for supplying the external input X, signal lines 102 for supplying the external output Z, signal lines 107 for supplying the feedback input Y', signal lines 108 for supplying the flipflop-driving signals Y and signal lines 109 feeding back the output Y" of the register 2 to the input of the combinational circuit 1, and each of these signal lines 101, 102, 107, 108 and 109 transmits a plurality of signals. The integrated logic circuit 100 is a synchronous type and comprises signal line 104 for supplying a sync signal C from outside and signal lines 105 for supplying an initializing signal R to initialize the integrated logic circuit 100.

#In order to distinguish testing from routine operation, a signal line 103 is provided for supplying a mode switching signal A to command switching between the routine operation and testing modes. A random signal generator 3 generates a random signal for the testing purpose. A multiplexer 4 selectively supplies the combinational logical circuit 1 with one of the random signal from the random signal generator 3 and the output Y" from the register 2, respectively supplied through signal lines 106 and 109. A signal line 110 is provided for leading out the test result from the register 2.

Facts

Application

06/130,687Filed 17 Mar 1980

Priority

JP 54-3024315 Mar 1979

Granted

28 Dec 1982

Term ended

17 Mar 2000

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification3 codes

G01R 31/318547
Scanning methods, algorithms and patterns: data generators or compressors
G01R 31/318516
Reconfiguring for testing, e.g. LSSD, partitioning: test of programmable logic devices [PLDs]
G01R
Measuring electric variables

Integrated logic circuit adapted to performance tests

Life of this patent

Integrated logic circuit adapted to performance tests

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims9

Description4,981 words

Drawings

Classification3 codes

Life of this patent

Description4,981 words