Compensating semiconductor materials
AssigneeMassachusetts Institute of Technology
InventorsGeorge W. Turner, John C. C. Fan, Jack P. Salerno
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AssigneeMassachusetts Institute of Technology
InventorsGeorge W. Turner, John C. C. Fan, Jack P. Salerno
Estimating the term…
A method of compensating grain boundaries or dislocations causing interstices to form particularly in polycrystalline semiconductor materials is disclosed which comprises selectively diffusing opposite impurity-type donor semiconductor material into the interstice to thereby reduce the conductivity of the interstice.
A compensation method for reducing the conductivity associated with the interstices formed in layers of polycrystalline semiconductor material wherein said layers form rectifying junctions at their interface, comprising introducing dopant into the interstices of a first layer of opposite type conductivity to the conductivity associated with the interstices of a second layer and allowing said dopant to travel along said interstices from the first layer, across the rectifying junction between layers and into the second layer.
A device formed of semiconductor material and having a substrate, a first layer on said substrate of a certain type conductivity, a second layer on said first layer of opposite conductivity to said first layer and forming a junction therebetween, the improvement comprising compensating interstices in said second layer formed by introducing dopant into said second layer through interstices in the second layer and across said junction into the interstices of the first layer.
A photovoltaic cell comprising:
A compensation method for reducing the conductivity associated with the interstices formed in layers of semiconductor material, comprising introducing dopant into the interstice of opposite type conductivity to the conductivity associated with the interstice and wherein the semiconductor material is GaAs and the dopant is Sn.
Dependencies are inferred from the claim text.
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Photovoltaic cells having only PN homojunction potential barriers: comprising only Group III-V materials, e.g. GaAs,AlGaAs, or InP photovoltaic cells
Manufacture or treatment of devices covered by this subclass: passivating
Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials: polycrystalline semiconductors
Photovoltaic [PV] energy: solar cells from Group III-V materials
Term ended 9 Jan 2001 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention is in the field of semiconductor materials and more specifically semiconductor materials for photovoltaic cells.
Photovoltaic cells have been developed which generate electrical energy directly from sunlight. Typically, such cells have been fabricated from semiconductor materials containing a rectifying junction, such as a p-n junction or a Schottky barrier.
A number of problems have been encountered, however, in attempts to produce photovoltaic cells which would have wide acceptance for use in producing energy from sunlight. One of the problems has been the cost of producing such cells, which has heretofore been relatively high. In fact, the cost of photovoltaic cells has generally been considered to be severely limiting except in applications where cost is not a controlling factor, such as in space applications or generation of power in remote areas.
FIG. 1 is a cross-sectional view of a photovoltaic device employing polycrystalline materials suitably doped to provide a rectifying junction and containing grain boundaries passivated in accordance with the invention.
FIG. 2 is an enlarged view of the section circled in FIG. 1.
FIG. 3 is a schematic view of a photovoltaic cell in accordance with the invention.
Preferred embodiments of this invention will now be described in more detail with reference to the Figures.
FIG. 1 illustrates a photovoltaic device, based upon a rectifying junction 15 formed in polycrystalline semiconductor material. The device has a conducting substrate 10, which may be formed from a material such as graphite, molybdenum or tungsten. In some cases, the semiconductor itself can serve as a conducting substrate if it is appropriately doped. Successive layers 12, 14 and 16, respectively, of p.sup.+ -semiconductor material, p-semiconductor material, and n.sup.+ -semiconductor material, respectively, are deposited upon conducting substrate 10 by well known processes. Semiconductor layers 12, 14, and 16 are preferably formed from gallium arsenide, suitably doped to provide the desired electrical properties. Thus, semiconductor layer 12 may be gallium arsenide suitably doped with p-dopants such as zinc, cadmium, beryllium or magnesium to a carrier level of 10.sup.18 CC.sup.-1 or above; semiconductor layer 14 may be a gallium arsenide layer suitably doped with p-dopants to a carrier level of 10.sup.16 -10.sup.17 ; CC.sup.-1 and n.sup.+ -semiconductor layer 16 may be gallium arsenide suitably doped with n-dopants such as sulfur, selenium or silicon to a carrier concentration of 10.sup.17 CC.sup.-1 or above.
Grain boundaries or other dislocation defects form interstices 22 which extend through each of semiconductor layers 12, 14 and 16. Such interstices may originate in p.sup.+ -semiconductor layer 12, which is formed from polycrystalline material, and extend through layers 14 and 16. These interstices produce a shorting effect across junction 15. Thus, the open circuit voltage of the device is significantly less than would be the case if such grain boundaries were not present, and this results in a much lower photovoltaic conversion efficiency.