Process and device for phasing a local clock
AssigneeThomson-CSF
InventorMaurice Sauvanet
Life of this patent
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Abstract
The most favorable clock signal among n available signals which present equal successive phase shifts is selected by comparison with a synchronization burst. For this, a logic phase comparison is effected between the signals obtained by division by 2 of each of the n clock phases with the bits of the synchronization burst by averaging the comparison signal obtained over several bits, and the most favorable clock phase is selected, corresponding to a phase shift close to .pi., as being the one represented by a voltage level located within a determined interval F.
Claims15
A process for phasing a local clock, in which the most favorable clock signal is selected among n available signals of the same frequency having equal successive phase shifts, by comparison with a synchronization burst, wherein a logic phase comparison is effected between (a) signals obtained by the division of frequency by `of each of the n available clock phases and (b) the bits of the synchronization burst to obtain a comparison signal, wherein the comparison signal obtained is averaged over several bits of this synchronization burst, and wherein one of the n signals is selected which has a phase shift close to .pi., the improvement comprising selecting the most favorable clock phase as being the one represented by a voltage level which is located within an interval or "window" centered substantially on a value equal to half of the maximum probable value VM of the voltage forming the comparison signal, which maximum value would be obtained for the maximum phase shift 2.pi..
A process for phasing a local clock, wherein, in a first stage, a comparison is made with one part of the total number n of available clock phases, in accordance with any one of the preceding claims, so as to preselect a phase and wherein, in a second stage, improvement of the phasing is proceeded with.
A device for phasing a local clock providing n available clock phases with a synchronization burst comprising in combination:
- a divider by 2 of each of the n available clock phases,
- means for enabling each divider by 2, in relation with the changes of state of the synchronization burst,
- logic means for comparing between the two signals obtained at the output of each divider by 2 and the bits of the synchronization burst,
- a circuit connected to the output of said logic comparison means, and adapted to supply a voltage representing the average value of the comparison signal obtained over several bits,
- other comparison means, adapted to compare the above-mentioned voltage with determined levels,
- a sampling and memorization stage, associated with a priority logic, connected to the output of the other comparison means,
- a multiplexer whose data inputs receive the n available clock signals, and whose address inputs are connected to the outputs of the preceding stage.
Dependencies are inferred from the claim text.