US 4,365,319 AGranted

Semiconductor memory device

AssigneeFujitsu Limited

InventorYoshihiro Takemae

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Abstract

A semiconductor device, in which a redundancy memory cell array is incorporated with a main memory cell matrix. One memory cell array is selected by two kinds of decoders and drivers. When the redundancy memory cell array is selected by a decoder, the decoder disables one kind of the decoders and drivers directly and, as a result, the other kind of the decoders and drivers are also disabled.

Claims10

Dependent claims

A semiconductor memory device comprising:

a main memory cell matrix having a plurality of sub memory cell matrixes, each sub memory cell matrix having a plurality of memory cell arrays;
a redundancy memory cell array incorporated into said main memory cell matrix;
a first decoder means having a plurality of inputs for receiving a first sub-part of a first address information having n bits and a first clock signal and having a plurality of outputs, for selecting one memory cell array parallel to said redundancy memory cell array and within each said sub memory cell matrix, in accordance with said first sub-part, of said first address information, said outputs of said first decoder means triggered by said first clock signal;
a second decoder means having a plurality of inputs for receiving a second sub-part of said first address information having m bits and said outputs of said first decoder means and having a plurality of output drivers, for selecting one of said sub memory cell matrixes within said main memory cell matrix, in accordance with said second sub-part of said first address information, said output drivers of said second decoder means triggered by said outputs of said first decoder means and select one memory cell array within said memory cell matrix;
a third decoder means having a plurality of inputs for receiving said first address information having n+m bits and an output operatively connected to said redundancy memory cell array and to said first decoder means for selecting said redundancy memory cell array and disabling said second decoder means, in accordance with said first address information,
said output drivers of said second decoder means being disabled when said third decoder means selects said redundancy memory cell array;
and
a fourth decoder means having a plurality of inputs for receiving a second address information, for selecting one memory cell array perpendicular to said redundancy memory cell array within said main memory cell matrix and said redundancy memory array, in accordance with said second address information.

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Dependencies are inferred from the claim text.

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Abstract

A semiconductor memory device comprising:

a main memory cell matrix having a plurality of sub memory cell matrixes, each sub memory cell matrix having a plurality of memory cell arrays;
a redundancy memory cell array incorporated into said main memory cell matrix;
a first decoder means having a plurality of inputs for receiving a first sub-part of a first address information having n bits and a first clock signal and having a plurality of outputs, for selecting one memory cell array parallel to said redundancy memory cell array and within each said sub memory cell matrix, in accordance with said first sub-part, of said first address information, said outputs of said first decoder means triggered by said first clock signal;
a second decoder means having a plurality of inputs for receiving a second sub-part of said first address information having m bits and said outputs of said first decoder means and having a plurality of output drivers, for selecting one of said sub memory cell matrixes within said main memory cell matrix, in accordance with said second sub-part of said first address information, said output drivers of said second decoder means triggered by said outputs of said first decoder means and select one memory cell array within said memory cell matrix;
a third decoder means having a plurality of inputs for receiving said first address information having n+m bits and an output operatively connected to said redundancy memory cell array and to said first decoder means for selecting said redundancy memory cell array and disabling said second decoder means, in accordance with said first address information,
said output drivers of said second decoder means being disabled when said third decoder means selects said redundancy memory cell array;
and
a fourth decoder means having a plurality of inputs for receiving a second address information, for selecting one memory cell array perpendicular to said redundancy memory cell array within said main memory cell matrix and said redundancy memory array, in accordance with said second address information.

5 more elements