Modular terminal system using a common bus

In a data processing system having a plurality of functional circuit board modules communicating with each other over a system bus, with one of the modules containing a central processing unit (CPU), the improvement comprising:

• a microprocessor (60) on the CPU circuit board, said microprocessor having a given number of address lines;
• said system bus (20) having a greater number of address lines than the address lines from the microprocessor;
• and
• memory mapping means (74) on the CPU circuit board coupled between selected address lines from the microprocessor and selected address lines of the system bus, operative to decode the signals on the microprocessor address lines and generate related signals on a greater number of output lines which are coupled to the address lines of the system bus thereby expanding the number of addressable system locations that would otherwise be accessible by the CPU.

In a data processing system having a plurality of functional circuit board modules including a plurality of slave modules communicating with each other over a system bus, with one of said modules including a central process unit (CPU) utilizing a microprocessor, wherein the improvement comprises vectored interrupt circuitry (210) for the slave modules in the system to permit efficient prioritized communication between the CPU and selected slave modules, said vectored interrupt circuit including:

• latch means (240) coupled to data lines on the system bus, said latch containing a predetermined multibit code defining a vector associated with a particular memory location accessible by the CPU;
• an interrupt priority line (212) coupled in a daisy chain fashion to other slave modules in the system;
• first storage device means (214) for asynchronously storing an internally generated interrupt request from the slave module;
• second storage device means (224) having an input coupled to the output of said first storage device, an output, and a clock input operative to transfer information on the second storage device input to its output upon receipt of a signal at the clock input thereof;
• interrupt line gating means (226) having inputs coupled for receipt of said interrupt priority line and the output from said second storage device, said interrupt gating means having an output adapted to be coupled to the input of the interrupt line of the next slave module;
• and
• means for coupling a clock signal from the CPU to the clock input of said second storage device whereby to control the state of the interrupt priority lines of the other slave modules.

In a data processing system (10) having a plurality of functional circuit board modules (24, 26, 28, 32, 36) communicating with each other over a system bus (20), with one of said modules including a central processing unit (CPU) (22) utilizing a microprocessor (60), wherein the improvement comprises vectored interrupt circuitry (210) for selected slave modules in the system to permit efficient prioritized communication between the CPU and the slave modules, said vectored interrupt circuitry including:

• latch means (240) coupled to data lines on the system bus, said latch containing a predetermined multibit code defining a vector associated with a particular memory location accessible by the CPU;
• an interrupt priority line (212) coupled in a daisy chain fashion to other slave modules in the system;
• first storage device means (214) for asynchronously storing an internally generated interrupt request from the slave module;
• vectored interrupt request generating means (216) coupled to the output of said first storage device, operative to initiate an interrupt request of said CPU microprocessor;
• second storage device means (224) having an input coupled to the output of said first storage device, an output, and a clock input operative to transfer information on the second storage device input to its output upon receipt of a signal at the clock input thereof;
• means in the CPU for successively generating a clock (M1) signal and an interrupt acknowledge (INTA) signal over the system bus to the slave module vectored interrupt circuitry;
• interrupt line gating means (226) having inputs coupled for receipt of said interrupt priority line and the output from said second storage device, said interrupt gating means having an output adapted to be coupled to the input of the interrupt lines of another slave module;
• enabling gating means (236) having a plurality of inputs coupled for respective receipt of signals on said interrupt priority line, the output of said second storage device, and said interrupt acknowledge signal;
• whereby said second storage device changes state upon receipt of said clock signal thereby activating said priority line gating means to inhibit the daisy chain priority lines of the other slave modules and wherein said enabling gating means couples the multibit vector contained in the latch to the CPU upon receipt of the subsequently received interrupt acknowledge signal, said vector thus being supplied only after sufficient time has elapsed for the daisy chain priority lines to stablize.

A method of prioritizing interrupt requests from a plurality of slave modules in a data processing system having a central processing unit (CPU) module, said modules communicating with each other over a system bus, said method comprising:

• linking said slave modules together with a priority line in order of descending priority;
• generating an interrupt request of said CPU from one of said slave modules;
• responding to said interrupt request by the CPU generating sequential first and second signals to said slave modules;
• changing the state of the priority lines of the slave modules not requesting an interrupt upon detection of said first responsive signal from the CPU and simultaneously storing an indication that said one module has requested an interrupt of the CPU;
• and
• placing data on the system bus from said one module upon receipt of the subsequently received second signal from the CPU.

In a data processing system having a plurality of distributed central processing units (CPU's) connected over a bus (20), said system having means by which a calling CPU may communicate with a target CPU, the improvement comprising:

• a pair of storage devices (300, 302) in each of the CPU's in the system, said storage devices serving as a response port and interrupt register, respectively, which are commonly accessible by all of the CPU's in the system;
• means (IOWC) in the calling CPU to write a given code into the response port of the target CPU;
• means (316) in the target CPU for preventing a difference CPU from writing into the response port of the target CPU once it has been written into;
• means (IORC) in the calling CPU for reading the code in the response port of the target CPU;
• means (IOWC) in the calling CPU for generating a multibit vector only if the calling CPU has read the same code that it previously attempted to write into the response port of the target CPU;
• loading means (WRIR) in the target CPU for loading said multi-bit vector into its interrupt register;
• and
• means (IPIE) in the target CPU for reenabling its response port to receive codes from other CPU's once the target CPU has completed the execution of an instruction associated with the vector in its interrupt register.

A method of controlling interprocessor communication between a calling central processing unit (CPU) and a target central processing unit (CPU) in a data processing system having a plurality of CPU's, said method comprising:

• writing a preselected code into a first storage device in the target CPU by the calling CPU;
• reading the contents of said first storage device by the calling CPU;
• placing a multibit vector into a second storage location in said target CPU only if said calling CPU has read said preselected code from the first storage device in the target CPU;
• and
• causing the target CPU to interrupt further operation and execute an instruction associated with the multibit vector in said storage device.

In a data processing system having a central processing unit (CPU) utilizing a microprocessor (60) for emulating another type of processor that operates on software code having a greater number of bits per word than is executable by the microprocessor, wherein the improvement comprises:

• a plurality of latch means (402, 404) for storing data therein associated with a word of software code from said other processor;
• a programmable logic array (406) having a plurality of inputs coupled to said latch means and outputs coupled to internal data lines (100) of said microprocessor;
• and
• means (408) for simultaneously transferring the contents of said latch means to the inputs of said programmable logic array for generating a word having a number of bits executable by the microprocessor.