Back to results
US 4,365,263 AGranted
Semiconductor integrated circuit device composed of insulated gate field-effect transistor
AssigneeHitachi, Ltd.
InventorHiroto Kawagoe
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeHitachi, Ltd.
InventorHiroto Kawagoe
Estimating the term…
In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprises the fact that insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix. Gate input columns of the transistors are formed of polycrystalline silicon layers, and some of the transistors are enhancement type, while others are depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystalline silicon layers as a diffusion mask, and the depletion type transistors are formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.
A semiconductor integrated circuit matrix device having a plurality of insulated gate field effect transistors arrayed along rows and columns comprising:
A semiconductor read only memory circuit device having a plurality of insulated gate field effect transistors arranged along rows and columns comprising:
A semiconductor integrated circuit matrix device containing a plurality of insulated gate field effect transistors some of which are enhancement mode field effect transistors and some of which are depletion mode field effect transistors comprising:
Dependencies are inferred from the claim text.