Semiconductor image sensor
AssigneeHandotai Kenkyu Shinkokai
InventorJunichi Nishizawa
Life of this patent
Estimating the term…
Abstract
A semiconductor image sensor employing static induction transistors having a nonsaturating current-voltage characteristic providing a high degree of linearity over a wide range of optical input intensities and a high operating speed. A plurality of high resistance channel regions are formed on a substrate region. Low resistance semiconductor storage regions of the same conductivity type are formed on corresponding ones of the channel regions and gates which form controllable potential barriers are provided around the channel regions. An insulating film is formed over the low resistance storage regions. Electrically conductive bit line electrodes are formed over the insulating film and electrical conductive word lines are connected to corresponding ones of the gates.
Claims11
A semiconductor image sensor comprising:
- a low resistance semiconductor electrode region of a first electrical conductivity type;
- a plurality of high resistivity channel regions formed on said electrode region;
- low resistivity semiconductor storage regions of said first electrical conductivity type formed on corresponding ones of said channel regions;
- gate means for forming controllable potential barriers in corresponding ones of said channel regions;
- an insulating film formed on said low resistivity semiconductor storage regions;
- electrically conductive line electrodes formed on said insulating film;
- and
- electrically conductive control lines connected to corresponding ones of said gate means,
- said line electrodes, insulating film and semiconductor storage regions forming storage capacitors and optical input windows.
A semiconductor image sensor comprising:
- a low resistivity semiconductor substrate region of a first electrical conductivity type;
- a plurality of low resistivity semiconductor storage regions of a second electrical conductivity type forming a plurality of p-n junctions with said substrate region;
- a plurality of high resistivity channel regions formed on corresponding ones of said storage regions;
- low resistivity bit regions formed on corresponding ones of said chanel regions;
- electrically conductive bit lines connected to corresponding ones of said bit regions;
- gate means for forming controllable potential barriers in corresponding ones of said channel regions;
- and
- electrically conductive word means connected to said gate means,
- said substrate region and storage regions forming storage capacitors and said bit regions and bit lines having optical input windows.
A semiconductor image sensor formed in a semiconductor body having at least one main surface, and including a plurality of picture cells disposed in a matrix chape, wherein each picture cell comprises:
- a first semiconductor region of a first conductivity type, having a low resistivity and disposed adjacent to said main surface;
- a channel semiconductor region of said first conductivity type, having a high resistivity and disposed under said first semiconductor region;
- a second semiconductor region of a second conductivity type opposite to said first conductivity type, having a low resistivity and disposed adjacent to said channel semiconductor region to define at least part of the periphery of said channel semiconductor region;
- a third semiconductor region of said first conductivity type, having a low resistivity and disposed under said channel semiconductor region;
- means for forming an insulated electrode on said first semiconductor region and for forming an optical window for transmitting lights injected thereon into said semiconductor wafer;
- and
- the image sensor further comprising:
- selective bias source means connected to each cell for supplying a first and a second bias between said insulated electrode and said third semiconductor region the former of which depletes said first semiconductor region and the latter of which re-neutralize the same, and for supplying a third and fourth bias to said second semiconductor region the former of which isolates said first semiconductor region from said second semiconductor region even when the first semiconductor region is depleted and the latter of which electrically connects said first semiconductor region with said third semiconductor region.
Dependencies are inferred from the claim text.