Multi-frequency clock generator with error-free frequency switching
AssigneeGeneral Electric Company
InventorsDonald V. DiMassimo, John B. May
Life of this patent
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Abstract
A system clock generator includes circuitry for error-free switching of clock frequency. Frequency switching is necessary, for example, when the main power supply fails and to conserve standby battery energy the system is operated at a low clock frequency. Conversely, when the main power source is restored, system clock frequency must be returned to normal. The clock generator and switching circuitry comprise two bistable switch circuits and an RC (resistance-capacitance) oscillator made up of a NAND gate, an inverter, and an RC network. One of the bistable switch circuits includes means for detecting the presence of signals indicating the existence of a condition requiring frequency switchover.
Claims6
A dual frequency clock generator selectively providing output clock signals at first and second frequencies, comprising:
- a source of input clock signals;
- a first bistable switching circuit including an input and an output, a reset means for establishing a predetermined logic state at the circuit output, and clock input means coupled to said source of input clock signals for reproducing at the circuit output the logic level on the circuit input upon the occurrence of each positive voltage transition of said input clock signal;
- a second bistable switching circuit substantially identical to said first circuit further including set means coupled to the output of said first circuit for setting the output of said second circuit to the logic level on the output of said first circuit, the output of said second circuit also being coupled to said reset means of said circuit, and the input of said second circuit being provided with a frequency select signal for selecting said first or second frequencies;
- and
- an RC oscillator coupled to the output of said second circuit, said RC oscillator including means coupled to the clock input means of said second circuit for reproducing at the output of said second circuit said frequency select signal in response to which said clock generator produces an output clock signal at said first or second frequency.
Dependencies are inferred from the claim text.