Duty cycle generator with improved resolution

A digitized duty cycle generator comprising:

• first means for generating a clock pulse signal having a repetition rate f.sub.c ;
• counter means responsive to said clock pulse signal to cycle iteratively through a count of n;
• storage means for storing a binary value m where m<n, where m/n is the duty cycle, and where m has a variable value;
• and
• logic means comprising comparator means responsive to the instantaneous count of l in said counter means and the value m in said storage means when m is not an integer to produce a first logic level output signal when l<m and a second logic level output signal when l>m during first selected cycles of said counter means through said count of n;
• said logic means comprising said comparator means being further responsive to the instantaneous count l in said counter means and the value (m+1) when m is not an integer to produce said first logic level when l<(m+1) and said second logic level when l>(m+1) during second selected cycles of said counter means through said count of n;
• said logic means further responsive to the count l in said counter means and to the value m to produce said first logic level signal when l.ltoreq.m and said second logic level signal when l>m during all cycles of said counter means through said count of n when m is an integer.

A method for generating a digitized duty cycle pulse comprising the steps of:

• generating a clock pulse signal having a repetition rate f.sub.c ;
• counting said clock pulse signals in iterative cycles through a count of n;
• storing a variable binary value m where m<n, where m/n is the pulse duty cycle;
• comparing an instantaneous count l and the stored value m when m is not an integer to produce a first logic level signal when l<m and a second logic level output signal when l>m during first selected cycles of said count through said count of n;
• comparing an instantaneous count l and a stored value (m+1) when m is not an integer to produce said first logic level signal when l<(m+1) and said second logic level signal when l>(m+1) during second selected cycles of said count through said count of n;
• and
• supplying said first and second logic levels produced during said first and second cycles to a utilization means.