Apparatus for digital division computation

Apparatus for digital division computation for producing a quotient by performing successive multiplication operations comprising:

• control means comprised of sequential circuitry for performing digital divisional operations to obtain a reciprocal of a constant,
• divisor register means comprised of a row of associated flipflops for receiving and storing a digital divisor quantity B,
• dividend/quotient register means comprised of a row of associated flipflops for receiving and storing a digital dividend quantity A,
• means for simultaneously transmitting a digital divisor quantity B to said divisor register means and a digital dividend quantity A to said dividend/quotient register means,
• multiplication means for iteratively determining initially digital acceleration constants a.sub.i and secondly digital quantities q.sub.i computed successively from digital contents of a pseudoradix/q register comprised of two rows of associated flipflops,
• counter means comprised of structured circuitry which performs the operation of counting the number of signals with feedback loops responsive not only to its present input but also to inputs that may have been presented previously,
• adding means comprised of sequential logical circuitry which performs the operation of adding two digital quantities,
• multiplying means comprised of sequential logical circuitry which performs the operation of multiplying two digital quantities,
• determination logic a.sub.i means for determining the acceleration constant a.sub.i from the received digital quantity q.sub.i,
• said multiplication means being interconnected iteratively with said divisor register means to receive and store a digital pseudoradix D.sup.n and a digital quantity q.sub.i in said pseudoradix/q register,
• means for transmitting a signal from said control means to said determination logic a.sub.i means to initiate said iterative process to sequentially transmit a signal each time from said determination logic a.sub.i means,
• means for performing a digital evaluation process of the function q.sub.i+l =h.sub.n+i (q.sub.i,a.sub.i)=-{D.sup.n+l+i -(a.sub.i +1)(D.sup.n+i +q.sub.i)}/D.sup.l+i for i=0,1,2, . . . where q.sub.o =B-D.sup.n,
• said control means initiating said counter means to count by one each time when said determination logic a.sub.i means sends a signal s(D-1>a.sub.i) when the condition D-1>a.sub.i occurs, said control means actuating said determination logic a.sub.i means to multiply the content of said dividend/quotient register by the digital quantity, one plus a digital acceleration constant from determination logic a.sub.i means,
• said iterative process continuing until a digital quantity q.sub.f, representative of the smallest possible fraction of B, is determined by performing a digital evaluation of the function q.sub.f =g.sub.n+i (q.sub.i,a.sub.i)={D.sup.n+l+i -a.sub.i (D.sup.n+i +q.sub.i)}/D.sup.n+l+i and a completion of the multiplying operation of the content of said dividend/quotient register by the acceleration constant when a signal s(D-1=a.sub.i) is generated by said determination logic a.sub.i means when the condition D-1=a.sub.i occurs where q.sub.i and a.sub.i denote the last iterative values,
• said multiplication means actuating said control means to bypass said iterative process when a signal s(D-1>a.sub.o) is generated from said determination logic a.sub.i means when the condition D-1>a.sub.o occurs, namely when the present content of said pseudoradix/q register which contains said quantity q.sub.o becomes said quantity q.sub.f,
• a determination logic b.sub.k means which, upon receipt of digital quantity q.sub.f, is activated by said control means to sequentially provide a digital acceleration factor b.sub.k by the process of a squaring operation Q.sub.k+l =Q.sub.k.sup.2 and adding operation b.sub.k =1+Q.sub.k+l for k=0,1,2, . . . where b.sub.o =1-q.sub.f and Q.sub.o =q.sub.f, and
• means for transmitting said acceleration factor b.sub.k to said dividend/quotient register means to sequentially multiply it with the present content of said dividend/quotient register means until a predetermined digital accuracy of the quotient has been accumulated when a signal s(Q.sub.k+l .ltoreq.C) is generated by said determination logic b.sub.k means when the condition Q.sub.k+l .ltoreq.C occurs where C denotes a digital quantity less than the least significant digit of said divisor register.