Multi-layered metallized silicon matrix substrate
AssigneeInternational Business Machines Corporation
InventorsHarold D. Edmonds, Gary Markovits
Life of this patent
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Abstract
A multi-layer metallized substrate comprises a matrix of sintered silicon particles joined by a thin insulating layer of silicon dioxide or silicon nitride. Semiconductor circuit chips are bonded to the surface of the substrate to form an electrically connected, unitary integrated circuit module structure.
Claims5
A substrate having a coefficient of expansion in the range of 2.5.times.10.sup.-6 to 4.1.times.10.sup.-6 .degree.K.sup.-1 comprising
- a matrix of sintered silicon particles of a size less than 5 microns, each particle joined and surrounded by an electrically insulating layer of a silicon compound selected from the group consisting of silicon dioxide, silicon nitride, and mixtures thereof, said insulating layer of a thickness in the range of 0.1 to 1 micron,
- said substrate including conductor lines formed therein, and having electrical connection pads on a surface thereof.
An integrated circuit module with at least one silicon semiconductor integrated circuit chip having electric conductors on a surface thereof, and a multi-layer laminated substrate having a coefficient of expansion in the range of 2.5.times.10.sup.-6 to 4.1 .times.10.sup.-6 .degree.K.sup.-1 comprising,
- a matrix of sintered silicon particles of a size less than 5 microns, each particle joined and surrounded by an insulating layer of a silicon compound selected from the group consisting of silicon dioxide, silicon nitride, and mixtures thereof, said insulating layer of a thickness in the range of 0.1 to 1 micron, said substrate having conductor lines formed therein and having electrical connection pads at a surface thereof, said electrical conductors and said pads being bonded together to form an electrically connected unitary structure.
Dependencies are inferred from the claim text.