US 4,364,091 AGranted

Equalizing pulse removal circuit

AssigneeTokyo Shibaura Denki Kabushiki Kaisha

InventorsShinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara

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Abstract

There are provided circuits for removing the equalizing pulses from the video signal. A composite sync signal separated from a video signal is applied to a gate circuit, so that only horizontal sync pulses are extracted. The gate pulse applied to the gate circuit is formed in the following manner. Clock pulses of a frequency 175/4 f.sub.H (f.sub.H : a horizontal scanning frequency and about 15,734 KHz), for example, is frequency-divided into a signal of a frequency 175/256 f.sub.H by a frequency divider. A reset circuit processes the frequency-divided output signal, the delayed sync signal and the inverted composite sync signal to form pulses in synchronism with the horizontal sync pulses. The pulses thus obtained reset the frequency divider. At the same timing of the pulse generation from the reset circuit, a gate pulse generating circuit generates pulses whose pulse widths are longer than the pulse widths of the horizontal pulses, which in turn are applied as the gate pulse to the gate circuit.

Claims2

Dependent claims

An equalizing pulse removal circuit comprising:

a first input terminal to which clock pulses with a higher frequency than the horizontal frequency are applied;
a frequency dividing circuit which frequency-divides the clock pulses applied to said input terminal into a signal with a frequency higher than 1/2H but lower than 1H;
a second input terminal to which a composite sync signal separated from a video signal is applied;
a delay circuit for delaying said composite sync signal applied to said second input terminal;
an inverting circuit for inverting said composite sync signal applied to said second input terminal;
a reset circuit which forms pulses synchronized with horizontal synchronized pulse included in said composite sync signal by using the output signals from said frequency dividing circuit, said delay circuit and said inverting circuit and for resetting said frequency dividing circuit;
a gate pulse forming circuit for forming gate pulses with a fixed pulse width which is longer than said horizontal synchronizing pulse width but shorter than 1/2H at the timing of the resetting of said frequency dividing circuit;
and
a gate circuit for allowing the composite sync signal applied to said second input terminal to pass therethrough only during a period that said gate pulse forming circuit produces gate pulses.

6 more elements

Dependencies are inferred from the claim text.