Thermal recording apparatus

A thermal recording apparatus comprising:

• a plurality of thermal resistive elements placed in a line;
• a plurality of drive circuits connected to said thermal resistive elements for driving corresponding ones of said thermal resistive elements;
• a plurality of latch circuits connected to said drive circuits for supplying recording signals to corresponding ones of said drive circuits;
• a first shift register for receiving and storing incoming recording signals which are input in series and formed by 1 and 0 signals, said first shift register supplying the incoming recording signals to said lach circuits;
• a second shift register coupled to an output of said first shift register for receiving previously received recording signals from said first register and storing the previously received recording signals;
• and
• a comparator connected to said first and second shift registers for comparing the incoming recording signals with the previously received recording signals bit by bit to generate modified recording signals, the modified recording signals including 0 signals which are generated by said comparator when 1 signals in the previously received recording signals follow 1 signals in the incoming recording signals, said comparator being coupled to said first shift register to supply the modified recording signals to said first shift register after the incoming recording signals are supplied to said latch circuits, said first shift register then supplying the modified recording signals to said latch circuits.

A thermal recording apparatus comprising:

• a plurality of thermal resistive elements placed in line;
• a plurality of drive circuits connected to said thermal resistive elements for driving corresponding ones of said thermal resistive elements;
• a plurality of latch circuits connected to said drive circuits for supplying recording signals to corresponding ones of said drive circuits;
• a first memory for receiving and storing incoming recording signals which are input in series and formed by 1 and 0 signals, said first memory supplying the incoming recording signals to said latch circuits;
• a second memory coupled to an output of said first memory for receiving recording sighals from said first memory and storing the previously received recording signals;
• a comparator connected to said first and second memory for comparing the incoming recording signals with the previously received recording signals to generate modified recording signals, the modified recording signals including 0 signals which are generated by said comparator when 1 signals in the incoming recording signals follow 1 signals in the previously received recording signals;
• and
• a third memory coupled to an output of said comparator for storing the modified recording signals, said third memory supplying the modified recording signals to said latch circuits after the incoming recording signals are supplied to said drive circuits.