US 4,364,036 AGranted

Composite logic analyzer capable of data display in two time-related formats

AssigneeIwatsu Electric Co., Ltd.

InventorKazunari Shimizu

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Abstract

A combined logic timing and state analyzer comprises an internally clocked, timing analyzer section receiving a first set of logic signals, and an externally clocked, state analyzer section receiving a second set of logic signals. The timing analyzer section samples the first set of logic signals, as well as the external clock signal associated with the second set of logic signals, at a rate determined by the internal clock pulses and stores the samples in a first set of memories. The state analyzer section samples the second set of logic signals at a rate determined by the external clock pulses and stores the samples in a second set of memories. Data introduction into the memories terminates when they are triggered, as in the event of a malfunction of the system being investigated. The logic analyzer further includes a display circuit for repetitively reading out the first and the second sets of memories and for causing a display device to visually present the output data of the first memory set in the form of a timing diagram and the output data of the second memory set in the form of a state table. The time relationship between the two display formats can be readily ascertained since the timing diagram includes a waveform, or other visual representations, indicative of the external clock pulses used for sampling the second set of logic signals.

A composite logic analyzer capable of displaying a first and a second set of data in different, time-related formats, comprising:

(a) first input means for receiving a first set of logic signals;
(b) second input means for receiving a second set of logic signals;
(c) additional input means for receiving an external clock signal associated with the second set of logic signals;
(d) an internal clock for generating an internal clock signal having a repetition frequency higher than that of the external clock signal;
(e) first sampler means coupled to the first input means for sampling the first set of logic signals at a rate determined by the internal clock signal;
(f) second sampler means coupled to the second input means for sampling the second set of logic signals at a rate determined by the external clock signal;
(g) additional sampler means coupled to the additional input means for sampling the external clock signal at a rate determined by the internal clock signal;
(h) first memory means coupled to the first sampler means for storing the samples of the first set of logic signals under the control of the internal clock signal;
(i) second memory means coupled to the second sampler means for storing the samples of the second set of logic signals under the control of the external clock signal;
(j) additional memory means coupled to the additional sampler means for storing the samples of the external clock signal under the control of the internal clock signal;
(k) trigger means coupled to the first, the second and the additional memory means for triggering same and hence for suspending the introduction of the samples therein;
(l) a display circuit coupled to the first, the second and the additional memory means for producing a first set of display signals for displaying in a first format the data recovered from the first and the additional memory means, and for producing a second set of display signals for displaying in a second format the data recovered from the second memory means;
and
(m) a display device coupled to the display circuit for making visual presentation of the output data in response to the first and the second sets of display signals.

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Abstract

Claims9