Reduced power tristate driver circuit
AssigneeRockwell International Corporation
InventorGary L. Heimbigner
Life of this patent
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Abstract
A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a first logic gate powered by a first buffer switch, a second logic gate powered by a second buffer switch, an output driver having a first driver input from the output of the first gate and a second signal driver input from the output of the second gate; the first and second buffer switches dissipating the greatest circuit power during the circuit float state operation, and means, coupled to the first and second buffer switches and to the source of float signal input signal, for interrupting power to the first and second buffer switches responsive to onset of the float state operation.
Claims17
A tristate driver circuit adapted to operate between a power source and a reference potential comprising:
- a signal source means having
- means providing an input signal,
- means providing a complement input signal,
- means providing a float input signal,
- means providing a complement float input signal;
- a first gate;
- a second gate, each said first and second gate having:
- a power gate input terminal adapted to be coupled to said power source,
- a first signal gate input terminal,
- a second signal gate input terminal, and
- a gate output terminal;
- a first buffer switch, a second buffer switch, each said first and second buffer switches having:
- a control electrode and a conduction path connected between said power source and said first and second gate power input terminals respectively;
- an output driver having:
- a first signal driver input terminal connected to said first gate output terminal,
- a second signal driver input terminal connected to said second gate output terminal,
- a driver output terminal;
- said first gate first signal gate input terminal being connected to said means providing a float input signal and to said second gate first signal gate input terminal,
- said first gate second signal gate input terminal being connected to said means providing an input signal and to said second buffer switch control electrode,
- said second gate second signal gate input terminal being connected to said means providing a complement input signal and to said first buffer switch control electrode;
- and
- means for interrupting power to said first and second conduction paths of said first and second buffer switches responsive to a signal from said complement float input signal means.
A tristate driver circuit adapted to operate between a power source and a reference potential comprising:
- a signal source means having
- means providing an input signal,
- means providing a complement input signal,
- means providing a float input signal,
- means providing a complement float input signal;
- a first NOR gate;
- a second NOR gate, each said first and second NOR gate having:
- a NOR gate power input terminal adapted to be coupled to said power source,
- a first signal gate input terminal,
- a second signal gate input terminal, and
- a gate output terminal;
- a first buffer switch, a second buffer switch, each said first and second buffer switches having:
- a control electrode and a conduction path connected between said power source and said first and second NOR gate power input terminals respectively;
- an output driver having:
- a first signal driver input terminal connected to said first gate output terminal,
- a second signal driver input terminal connected to said second gate output terminal,
- a driver output terminal;
- said first NOR gate first signal gate input terminal being connected to said means providing a float input signal and to said second NOR gate first signal gate input terminal,
- said first NOR gate second signal gate input terminal being connected to said means providing an input signal and to said second buffer switch control electrode,
- said second NOR gate second signal gate input terminal being connected to said means providing a complement float input signal and to said first buffer switch control electrode;
- and
- means for interrupting power to said first and second conduction paths of said first and second buffer switches responsive to a signal from said complement float input signal means, said first and second NOR gates, said first and second buffer switches, said output driver, and said means for signal responsively interrupting power to said first and second conduction paths of said first and second buffer switches each comprise FET transistors.
In a tristate driver circuit for operation between a voltage source and a reference potential such as ground and being particularly adapted for fabrication exclusively from n-channel field effect transistors or exclusively from p-channel field effect transistors and being adapted to receive an input signal and a complement input signal to produce a logic one output level or a logic zero output level and being further adapted to receive a float input signal and a complement float input signal to produce float state operation, the circuit comprising:
- a first logic gate having a first and second signal gate input terminal, a power gate input terminal, and an output terminal,
- a second logic gate having a first and second signal gate input terminal, a power gate input terminal, an output terminal,
- a first and second buffer switch, each said buffer switch having a conduction channel having a respective first and second terminal and a control grid, said first buffer switch conduction channel second terminal being connected to said first logic gate power gate input terminal, said second buffer switch conduction channel second terminal being connected to said second logic gate power gate input terminal,
- an output driver having a first signal driver input from the output terminal of said first logic gate and a second signal driver input from the output terminal of said second logic gate,
- said first buffer switch control grid being connected to said second logic gate second signal gate input terminal and also coupled to said complement input signal,
- said second buffer switch control grid being connected to said first logic gate second signal gate input terminal and also connected to said input signal,
- said first and second logic gate first signal gate input terminals being coupled to said float input signal,
- means for interrupting power from said voltage source to said respective first and second buffer switch conduction channel first terminals, said means for interrupting power having a first and second terminal, a complement float input signal terminal and a power input terminal, said means for interrupting power first terminal being connected to said first buffer switch conduction channel first terminal, said means for interrupting power second terminal being connected to said second buffer switch conduction channel first terminal, said power input terminal being connected to said voltage source, said complement float input signal terminal being connected to said complement float input signal, said means for interrupting power being responsive to said complement float input signal;
- whereby, said means for interrupting power operates to reduce the power dissipation of said first and second buffer switches at the onset of said float state operation.
Dependencies are inferred from the claim text.