Dummy cell arrangement for an MOS memory

In an MOS memory having a plurality of memory cells each having a memory cell capacitor of a given size which is adapted to be charged so as to reflect the logic state of its memory cell, and having a plurality of bit lines for accessing a particular memory cell, a dummy cell arrangement for sensing the state of an accessed memory cell, comprising:

• a plurality of sense amplifiers, each of which is coupled to two pairs of bit lines so as to sense potentials on a selected one of either of the pairs of bit lines to which it is coupled, and to latch in a logic state indicative of the difference between the potentials on the sensed pair of bit lines;
• means for selectively coupling the memory cell capacitor associated with the accessed memory cell to one bit line sensed by first sense amplifier so as to effect a transfer of charge between said one bit line and the memory cell capacitor;
• a plurality of dummy cells each having a dummy capacitor of substantially the same given size as a memory cell capacitor and each adapted to be precharged to a selected voltage level;
• and
• means for selectively coupling a selected dummy cell capacitor to the other of the bit lines sensed by said first sense amplifier, and to another bit line which is coupled to another sense amplifier, such that the selected dummy capacitor appears as half said given value to each of the two bit lines to which it is coupled and said first sense amplifier detects a resultant difference in voltage between its sensed bit lines and latches in a state indicative of that difference.

In an MOS memory having a plurality of memory cells each having a memory cell capacitor of a given size which is adapted to be charged so as to reflect the logic state of its memory cell, and having a plurality of word lines and bit lines for accessing a particular memory cell, a dummy cell arrangement for sensing the state of an accessed memory cell, comprising:

• a plurality of sense amplifiers, each of which is coupled to two pairs of bit lines so as to sense potentials on a selected one of either of the pair of bit lines to which it is coupled, and each of which receives a latch signal to enable it to latch in one of two logic states indicative of the difference between the potentials on the sensed pair of bit lines;
• means for coupling the capacitor associated with the accessed memory cell to one of the bit lines being sensed by a first sense amplifier in response to a signal of a given level being applied to a selected word line so as to effect a transfer of charge between said one bit line and the memory cell capacitor;
• a plurality of dummy word lines;
• a plurality of dummy cells each having a dummy capacitor of substantially the same given size as a memory cell capacitor and adapted to be precharged to a selected voltage level;
• means for coupling a selected dummy cell capacitor to the other of the bit lines sensed by said first sense amplifier and to another bit line which is coupled to another sense amplifier in response to a dummy word line signal of said given level being applied to a selected dummy word line such that the selected dummy capacitor and the memory cell capacitor transfer equal values of charge between their respective word lines and the sensed bit lines and such that the selected dummy capacitor appears as half said given value to each of the two bit lines to which it is coupled, and said dummy word line signal being selected to assume another level no sooner than the latch signal is applied to said first sense amplifier for decoupling the selected dummy capacitor from the sensed bit line.