Non-volatile dynamic RAM cell

A non-volatile dynamic random access memory cell comprising;

• a semiconductor substrate,
• a storage capacitor having a plate and a storage node disposed in said substrate,
• means for applying a first reference voltage to said plate, said first reference voltage having a first magnitude during one period of time and a second magnitude substantially greater than said first magnitude during another period of time,
• a control electrode,
• means for applying a second reference voltage to said control electrode, said second reference voltage having a first magnitude during said one period of time and a second magnitude substantially smaller than said first magnitude of said second reference voltage during said another period of time,
• a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to the common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said storage node,
• a bit/sense line disposed in said substrate, and
• a field effect transistor disposed between said storage node and said bit/sense line.

A dynamic memory cell comprising;

• a semiconductor substrate,
• a storage capacitor having a capacitor electrode and a storage node disposed in said substrate,
• a control electrode,
• means for applying control voltages between said control electrode and said capacitor electrode,
• a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to the common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said storage node,
• a bit/sense line, and
• a transfer device disposed between said storage node and said bit/sense line.

A dynamic memory cell comprising;

• a semiconductor substrate,
• a storage capacitor having a capacitor electrode and a storage node disposed in said substrate,
• a control electrode,
• means for applying control voltages between said control electrode and said capacitor electrode,
• a floating gate disposed between said control electrode and said storage node,
• an enhanced conduction insulator disposed between said control electrode and said storage node,
• a bit/sense line, and
• a transfer device disposed between said storage node and said bit/sense line.

A memory cell comprising;

• a storage capacitor having a storage node and a plate,
• a control electrode,
• a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to the common point between said first and second capacitors said voltage divider circuit being disposed between said control electrode and said storage node, and
• means for applying control voltages to said control electrode and to said plate.