Low cost programmable video computer terminal

A low cost computer terminal apparatus for entering data and for transmitting data to and receiving data from another data processing device and for displaying data comprising:

• (a) keyboard means comprised of a plurality of character and control switches arranged in matrix, said keyboard means having one side of the switches in each column coupled to a scan line and having a second side of the switches in each row coupled to a sense line, said keyboard means allowing an operator to send character data and control signals to said computer terminal by causing a binary data byte to appear on said sense lines for every distinct combination of character or control switch activation and binary data byte on said scan lines;
• (b) modem means for coupling said computer terminal to said other data processing device over a long distance communication system, said modem means including apparatus for converting binary data from said computer terminal into signals suitable for transmission over said long distance communication system into binary data for use by said computer terminal, said modem means having a data input to receive data to be sent to said other data processing device and a data output for sending data to said computer terminal;
• (c) parallel port means for coupling said computer terminal to another data processing device via a plurality of parallel lines, said parallel port means including apparatus for carrying data signals to and from said other data processing device, said parallel port means having an input register for receiving and holding data from said other data processing device, said input register including apparatus for setting a Portinbusy flag when said input register is loaded, said parallel port means including an output register for receiving and holding data from said computer terminal to be transmitted to said other data processing device, said output register including apparatus for setting a Portoutbusy flag when loaded;
• (d) memory means for storing data to be displayed by said computer terminal;
• said memory means having a data input for receiving the data to be stored in the write mode and a character data output for presenting data retrieved from storage for display in a read mode, wherein said character data to said other data output is selectively coupled to said output register of said parallel port means for allowing simultaneous display and transmission of character data to said other data processing device, wherein said selective coupling occurs under control of a Memro control signal, said memory means having an address input for receiving the address to store said data in said write mode, said memory means receiving the address from which to retrieve said data in the read mode, said memory means having a control input for receiving a $MEM control signal causing said read mode or said write mode to be selected;
• (e) switching means for switching the address at either of two inputs to an output coupled to said address input of said memory means, each of said two inputs receiving an address byte, said switching means having a control input for receiving an ISW control signal for causing switching of said inputs;
• (f) clock means for providing a stable timing waveform;
• (g) dividing counter means for counting the periods of said timing waveform and for generating an Advhosp signal after every Nth period of said timing waveform, wherein N is a predetermined number indicating one character display time has elapsed;
• (h) a television monitor for displaying the video data contained in a composite video signal applied to an input to said television;
• (i) a means for generating said composite video signal comprising;
• (1) horizontal address counter means for counting the periods of said Advhosp signal, said horizontal address counter means generating an Hsync signal at the end of every line traced by said television monitor for synchronization of the horizontal sweep oscillator in said television monitor, said horizontal address counter means also generating a Line Active signal for blanking the television monitor display to the right and left of the lines of characters or graphics data being displayed, wherein said horizontal address counter means generates a binary representation of the count of said Advhosp signal periods as the horizontal address output representing the horizontal address of the data byte are being displayed, said horizontal address counter means being coupled to a portion of one of said inputs of said switching means for supplying the horizontal portion of the address of the character to be retrieved by said memory means in the read mode;
• (2) vertical address counter for counting the occurrences of said Hsync signal, said vertical address counter generating a binary representation of the count as the vertical address output byte indicating the line said television monitor is displaying, wherein said vertical address counter generates an interrupt request signal after every Mth line, where M is a predetermined number, said vertical address output also being coupled to the remaining portion of the input of said switching means coupled to said horizontal address output;
• (3) character generator means for storing a plurality of groups of binary bytes, each group of bytes representing a character which can be displayed by said computer terminal, each of said characters comprised of a dot matrix of light and dark dots with each group of binary bytes having one byte representing each row in said dot matrix, said character generator means having a character data input coupled to said character data output of said memory means for receiving character data of the character to be displayed to serve as the address for the particular matrix to be displayed one row at a time, said character generator means having an input for receiving a portion of the vertical address output byte, said portion serving to control which row of said matrix to display, said character generator means having a dot line output from which to send a dot line byte representing one row of the dot matrix being displayed;
• (4) a character shift register having a parallel load input coupled to said dot line byte output and a video output, said character shift register also having a clock input coupled to said clock means, said character shift register receiving said dot line byte in parallel format and shifting it out from said video output in synchronization with said clock means in serial format as the video data component of said composite video signal;
• (5) a video status register having a data bus input and Vert Sync and Blank outputs for receiving data indicating when a vertical synchronization pulse should occur in order to cause synchronization of the vertical sweep oscillator in said television set, said video status register also causing said Vert Sync output to assume a predetermined logical state upon the appearance of another predetermined logical state on said data bus, wherein said video status register receives data on said data bus indicating when vertical blanking of the display on the television set should occur and causes the Blank output to assume a predetermined logical state;
• (6) gating means coupled to said video output of said character shift register and to said Vert Sync and Blank outputs of said video status register and to said Hsync and Line Active signals from said horizontal address counter means, said gating means combining all the above signals into a single composite video signal to be sent to said television set;
• (j) digital processor means for controlling the input, output, and display functions of said computer terminal, said digital processor means having an address bus coupled to said scan lines of said keyboard means for periodically energizing each scan line, said digital processor means having a data bus selectively coupled to said sense lines for reading said data bytes, wherein said digital processor means encodes said data byte along with the information on said address bus into a distinctive character data code for each character and control character on said keyboard means, said digital processor means processing said data in accord with the entered commands of said operator, said data bus being coupled to said input and output registers and said Portinbusy and said Portoutbusy flags of said parallel port means, whereby said Portoutbusy flag is sensed by said digital processor means and said output register is loaded with data to be sent to said other data processing device, said digital processor means periodically testing the status of said Portinbusy flag and reading the data loaded into said input register by said other data processing device, wherein said digital processor means processes said data in accord with said entered commands, said digital processor means controlling when said character data output of said memory means is coupled to said output register by controlling said Memro signal, said digital processor means having a control output coupled to said modem means for supplying binary data to said modem means for transmission to said other data processing device, said digital processor means having a control input coupled to said modem means for sensing when data is being received by said modem, said digital processor means processing said data in accord with said entered commands, said processing under control of the operator by control characters entered from said keyboard means, wherein said processing includes the ability to take data from either the keyboard means, the modem means, or the parallel port means and send it to any combination of the television set, the parallel port means, and the modem means, said data bus coupled to said data input of said memory means for supplying the character data to be stored in said write mode, said address bus coupled to the other of said two inputs and to said switching means for supplying an address for storage of data in said write mode, wherein said digital processor means is responsive to said interrupt request from said vertical address counter for counting the number of interrupt requests and for setting and resetting said Vert Sync bit at two predetermined counts and said Blank bit at two predetermined counts via said data bus coupled to the input of said video status register, said digital processor means thereby controlling the display function.