US 4,363,095 AGranted

Hit/miss logic for a cache memory

AssigneeHoneywell Information Systems Inc.

InventorsWilliam E. Woods, Arthur Peters

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Abstract

In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

Claims13

Dependent claims

In a data processing system including a system memory for addressably storing a plurality of data words identified by a like plurality of associated odd and even address numbers, each address number including a first portion and a second portion, and wherein system elements generate requests for the transfer of a pair of data words identified by successive address numbers, a transfer request including a memory request address number identifying the first of the pair of data words requested, a cache memory for selectively storing a subset of the data words stored in the system memory and for supplying the requested data words in the place of the system memory if the requested data words are stored in the cache memory, the cache memory comprising:

memory means for storing said subset of said data words stored in said system memory, said memory means including an odd memory module for storing said data words identified by said odd address numbers and an even memory module for separately storing said data words identified by said even address numbers;
an odd directory memory for storing said address numbers identifying said data words stored in said odd memory modules;
an even directory memory for storing said address numbers identifying said data words stored in said even memory modules;
means for receiving each of said address numbers supplied by said system elements and for determining if said received memory request address number and the next successive address number are stored in said odd or even directory memories;
and
hit detector circuit means coupled to said receiving and determining means for generating a full hit signal if both said supplied memory request address number and said next successive address number are determined to be stored in said odd and even directory memories, a partial hit signal if only one of said supplied memory request address number and said next successive address number are determined to be stored in said odd and even directory memories, and a no hit signal if neither said supplied memory request address number nor said next successive address numer are determined to be stored in said odd and even directory memories.

3 more elements

In a data processing system including a system memory for addressably storing a plurality of data words identified by a like plurality of odd and even address numbers having a first address portion and a second address portion wherein system elements supply a memory request address number also having first and second address portions when requesting a transfer of a pair of data words identified by successive address numbers, a cache memory comprising:

memory means for storing a subset of said data words stored in said system memory, said memory means including a plurality of memory locations, each said memory location for storing a said data word identified by one of a different plurality of address numbers, said plurality of memory locations being separated into an odd memory module for addressably storing said data words identified by said odd address numbers and an even memory module for addressably storing said data words identified by said even address numbers;
a directory memory module for storing in a second plurality of memory locations singly associated with said first plurality of memory locations the second address portions of said address numbers identifying said data words stored in said associated first plurality of memory locations, said second plurality of memory locations being separated into an odd directory for addressably storing said second address portions of said associated odd address numbers and an even directory for addressably storing said second address portion of said associated even address numbers;
means for receiving said memory request address numbers supplied by said system elements and for incrementing each of said received memory request address numbers by one such that said received memory request address number and said incremented address number comprise a pair of successive address numbers including an odd address number and an even address number;
means for comparing said second address portion of said even address number of said pair of address numbers to said second address portions of said address numbers stored in said even directory to determine whether said data word identified by a said even address number of said pair of address numbers is stored in said even memory module, and for comparing said second address portion of said odd address number of said pair of address members to said second address portions of said address numbers stored in said odd directory to determine whether said data word identified by said odd address number of said pair of address numbers is stored in said odd memory module;
and
hit detector circuit means coupled to said comparing means for generating a full hit signal if said comparing means determines that said data words identified by said pair of address numbers are both stored in said memory means, a partial hit signal if said comparing means determines that said data word identified by only one of said pair of address numbers is stored in said memory means, and a no hit signal if said comparing means determines that neither of said data words identified by said pair of address numbers is stored in said memory means.

3 more elements

Dependencies are inferred from the claim text.