Communications processor

An information transfer system for transferring information between a group of at least three independently operating asynchronous information processing means and a common information storage and retrieval device comprising:

• information bus means including plural bi-directional data lines, plural address lines, and plural bus control lines,
• said group of independently operating information processing means each coupled to said plural bi-directional data and address lines and at least some of said bus control lines,
• arbitrator means coupling said common information storage and retrieval device to said bi-directional data and address lines,
• said arbitrator means including bus clock generating means generating a substantially periodic signal having two distinctive portions, said bus clock means coupled through one of said bus control lines to a plurality of said independently operating information processing means, and further including a bus grant signal generating means for producing a bus grant signal,
• each of said plurality of independently operating information processing means including,
• information transmitting/receiving means coupled to said bi-directional data and address lines of said information bus means, and control means for selectively enabling said information transmitting/receiving means to transmit or receive information from said bus,
• said control means coupled to at least some of said bus control lines for enabling said transmitting means to transmit on said information bus means during one distinctive portion of said periodic signal but only in response to receipt of said bus grant signal prior to said one distinctive portion of said periodic signal and, substantially simultaneous with initiation of said transmission, to output a replica of said bus grant signal if the associated information processing means requires access to said information storage and retrieval device, said control means responding to receipt of a bus grant signal to substantially simultaneously therewith output a replica of said bus grant signal if the associated information processing means does not require access to said information storage and retrieval device,
• said bus control lines of said bus means including a means coupling said bus grant signal to be effective at only one of said plurality of independently operating information processing means, and further including additional means coupling a bus grant output of said one independently operating information processing means to be effective at only a control means of another independently operating information processing means.

A method of distributing access to a common bus among a plurality of independently operating data processors each of which can both transmit to and receive from said common bus for the purpose of allowing said data processors to access a common memory device coupled to said bus, the method comprising the steps of:

• (1) distributing a cyclic bus timing signal and allowing transmission from any data processor only during a first portion of said timing signal and allowing reception by any said data processor during another portion of said timing signal, exclusive of said first portion
• (2) generating a control signal when said processors collectively have had, refused or do not require access and coupling said signal to only one of said data processors,
• (3) transmitting from any processor in response to receipt of said control signal, said transmission synchronous with said first distinctive portion and simultaneous with said transmission coupling said control signal to a control signal output, and
• (4) coupling said control signal from a control signal output of one data processor to another in a predetermined order.

A communication processor including common memory means,

• a bidirectional demand assigned information bus means providing access to said memory means,
• a plurality of at least three independently operating asynchronous microprocessors each coupled to said demand assigned information bus means,
• arbitrator means and a plurality of bus access means each of said bus access means associated with a different one of said microprocessor for controlling access to said bidirectional demand assigned information bus means by said microprocessors jointly with all other bus access means and said arbitrator means,
• memory bus means coupled between said arbitrator and said memory means, said arbitrator means coupled to said bidirectional demand assigned information bus means and to said memory bus means for transferring information between both said bus means,
• a plurality of modems, each coupled to a different one of said microprocessors for the transfer of information therebetween and
• an executive microprocessor coupled to said bidirectional demand assigned information bus means and to said arbitrator,
• a plurality of interface switching means, each interface switching means coupling a modem to a different one of said plurality of independently operating microprocessors,
• common interface switching bus,
• a group of interface switching means also coupled to said common interface switching bus, logic means in each of said group of interface switching means, and means coupling said logic means to said executive microprocessor, said logic means responsive to controls from said executive microprocessor for coupling information from a modem onto said interface switching bus.

An information transfer system for transferring information between a common location and a plurality of at least three independently operating data processors including a bidirectional data and address bus operating in a demand assigned mode, comprising:

• bus grant signal generating means at said common location for generating a bus grant signal and for coupling said bus grant signal to a bus grant input of a bus access logic means associated with a single one of said independently operating data processors,
• a bus access logic means associated with each of said independently operating data processors for allowing said associated data processor access to said bidirectional data and address bus in response to receipt of said bus grant signal if said associated processor previously requested access to said data and address bus, each said bus access logic means including a bus grant input and a bus grant output,
• a control bus, means coupling said control bus to each said bus access logic means for distribution of a clocking signal to each bus access logic means, said control bus including a segmented bus grant conductor with different segments connected from a bus grant output of a bus access logic means to a bus grant input of another bus access logic means, so that each bus grant input is coupled to a bus grant output of a different bus access logic means except for that bus grant input coupled to said bus grant signal generating means,
• each said bus access logic means including a complete signal means for producing a distinctive output at an output terminal only when an associated data processor requires access to said data and address bus and for producing a different output at said terminal each time said associated data processor has had access to said data and address bus or does not require such access,
• said control bus including first means responsive to said output terminal of each said complete signal means to produce a first output when each said complete signal means does not produce said distinctive output,
• said bus grant signal generating means including logic means responsive to said first output of said first means for generating a bus grant signal each time said first means produces said first output.