Extended address, single and multiple bit microprocessor

A data processing system having at least one internal bus comprising:

• a memory for storing digital information having an addressable memory space;
• a first plurality of registers coupled to said internal bus for temporarily storing a corresponding plurality of single bytes of digital information;
• a second plurality of registers coupled to said internal bus for temporarily storing a corresponding plurality of multiple byte digital words having a maximum bit length;
• and
• control means coupled to said memory including an arithmetic/logic unit for performing selected arithmetic and logical operations upon digital information, and coupled to said first and second plurality of registers through said internal bus to selectively transfer digital information therebetween and to selectively generate a plurality of discrete command signals thereto in response to a plurality of instructions wherein said control means includes an extended address means for generating an extended digital word having a bit length greater than said maximum bit length, said extended address means being selectively coupled to said first and second plurality of registers, said extended digital word being generated by said extended address means from selected ones of said single bytes and multiple byte words stored in said first and second plurality of registers respectively.

An improvement for generating an address word for addressing an extended memory space, said improvement being in a data processing system including a memory unit for storing digital information and a processor unit, including an adder, for processing digital information communicated at least in part between said processor unit and said memory unit, said improvement comprising:

• a plurality of registers in said processor unit, said registers for storing words of digital information, at least some of said registers being relocation registers and the remainder being non-relocation registers, said relocation registers being selectively coupled by said processor unit to a first input of said adder, said non-relocation registers being selectively coupled by said processor unit to a second input of said adder such that a subset of bits of said word stored in said selected non-relocation register is numerically added by said adder to said word stored in said relocation register wherein the binary order of magnitude of said subset of bits is unequal to the binary order of magnitude of the bits of said word from said relocation register, the remaining bits of said word from said non-relocation register being appended to the sum of said adder to result in an address word greater in bit length than the maximum bit length stored in said plurality of registers,
• whereby said data processing system is afforded an extended memory space beyond the address word length limitation of said plurality of registers.

An improvement in a data processing system including a memory unit for storing digital information and a processor unit for processing digital information, said digital information including an instruction having a sign bit, 1 bit, and immediate data of word or byte length having lower and higher order bits comprising:

• means for recognizing the presence of a 1 bit in an instruction;
• means for determining whether an operation upon immediate data within an instruction has a word or byte length in response to said 1 bit;
• and
• means for extending the bit length of said immediate data to all higher order bit positions by copying said sign bit in all said higher order bit positions when said immediate data has a byte length so that operation upon said immediate data can be hardware identical regardless of the bit length of said immediate data.