Clock recovery apparatus for phase shift keyed encoded data
OwnerRobert M. Fullerinventor
Life of this patent
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Abstract
A pseudo clock generator produces pulses synchronous with, and having a period equal to one-half of the clock signal within a phase shift keyed encoded data stream. A phase lock circuit, having a stable period equal to that of the data clock signal tends to lock to the pseudo clock signal. Logic detects the condition of the phase lock signal being in phase lock with said data clock signal and in response thereto, masking circuitry prevents the pseudo clock generator from responding to input data transitions which occur outside of a predetermined masking window.
Claims10
Apparatus for recovering the clock signal, of predetermined period T, within a predetermined phase shift keyed encoded input data signal comprising:
- pseudo clock signal means for producing a pseudo clock signal having a period T and having a transition corresponding to said input data signal;
- phase lock means including:
- oscillator means for producing a phase variable signal having said predetermined period T;
- and
- phase comparator means for comparing the phase of said oscillator means produced signal with the phase of said pseudo clock signal and causing the phase of said oscillator means produced signal to tend to lock with said pseudo clock signal;
- logic means for producing a lock signal responsive to said oscillator means produced signal being in phase lock with the clock signal of said encoded input data signal;
- and
- masking means being responsive to a produced lock signal for producing a masking signal having a predetermined time duration t, where t.ltoreq.T/2, with t/2 of said masking signal being on either side of the transitions of said pseudo clock signal, and masking circuitry for preventing said pseudo clock signal from responding to input data signal transitions which occur outside of said masking signal duration,
- whereby said oscillator means produced signal comprises said recovered clock signal.
Apparatus for producing a pseudo clock signal recreating the clock signal, of predetermined period T, within a predetermined phase shift keyed encoded input data signal comprising:
- timing pulse means for producing, synchronous to the occurrence of an input data transition, a timing pulse having a period T/2;
- inhibit pulse means for producing, synchronous to the occurrence of an input data transition, an inhibit pulse having a predetermined period T.sub.I, where T/2<T.sub.I <T;
- and
- inhibit means for inhibiting the production of a timing pulse during said period T.sub.I of said inhibit pulse,
- whereby said timing pulses comprise said pseudo clock signal.
Dependencies are inferred from the claim text.