Quadriphase differential demodulator

In a differentially encoded phase-modulation data transmission system in which a carrier signal is phase-shifted over a data interval at a modulation rate to represent a pair of data bits for transmission to a receiver, a demodulator apparatus in the receiver for decoding the transmitted data comprising:

• means responsive to receiving said carrier signal for generating a first control signal representing the start of a data interval;
• means for generating a first clock signal operated in response to receiving said first control signal;
• means for generating a second clock signal having the same phase as said first clock signal in response to the generation of said first clock signal;
• means coupled to said second clock signal generating means for decoding the carrier signal to derive second and third control signals representing a perdetermined pair of data bits in response to receiving said second clock pulses;
• means coupled to said first clock signal generating means for outputting third clock signals adjusted to the phase of said first clock signals;
• a source of fourth clock signals;
• first switching means connected to said second clock signal generating means and receiving said third and fourth clock signals and operated to output either of said third or fourth clock signals to said second clock generating means;
• means coupled to said first switching means and responsive to the generation of said second and third control signals for operating said switching means to output said fourth clock signals to said second clock signal generating means;
• and means coupled to said operating means for counting the number of said predetermined pair of data bits decoded by said decoding means, said counter means controlling said operating means upon reaching a predetermined count whereby said first switching means outputs said third clock signals to said second clock signal generating means.

A method for synchronizing the demodulation of a differentially-encoded phase-modulated carrier signal in which the carrier signal is phase-shifted over a data interval to represent one of a plurality of pairs of data bits comprising the steps of:

• detecting the start of a data interval in the carrier signal;
• generating a first clock pulse representing the data interval upon detecting the start of the data interval;
• generating a second clock pulse representing approximately the data interval;
• adjusting the phase of the second clock pulse to the phase of the first clock pulse;
• demodulating the carrier signal in accordance with the phase of the second clock pulse to generate a first control signal representing a predetermined pair of data bits;
• disabling the adjusting step upon the generation of said first control signal;
• generating a predetermined count of the occurrences of said first control signals;
• and adjusting the phase of the second clock pulse to the phase of the first clock pulses (at the occurrence of each of said first control signals) upon the generation of said predetermined count.