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US 4,362,957 AGranted
Clock pulse tolerance verification circuit
AssigneeGTE Automatic Electric Labs Inc.
InventorDavid R. Stern
Life of this patent
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Abstract
A circuit arrangement for comparing a clock pulse train against a standard pulse train. The circuit includes an exclusive OR gate to which are inputted the pulse train to be tested, and a latch at the output of the gate, operated only upon a mismatch of the two pulse trains. Provision is also made to prevent operation of the latch within certain adjustable tolerance parameters as to pulse width and position of the pulse train.
Claims4
A system for verifying the presence synchronization and correct tolerance of a pulse train comprising:
- a source of standard pulses,
- an exclusive OR gate to which are inputted the pulse train to be tested and said standard pulses and having an output,
- a first and a second pulse generating means operated in response to said standard pulses to output a first tolerance pulse at an acceptable time ahead of the desired start time for a pulse of said tested pulse train and a second tolerance pulse at an acceptable time ahead of the desired termination for a pulse of said tested pulse train,
- a NAND gate having inputs connected to said exclusive OR gate output, and said first and second pulse generating means, and
- an error latch having as an input the output of said NAND gate whereby said latch is inhibited from operation during the presence of said tolerance pulses.
2 more elements
Dependencies are inferred from the claim text.