Bus-register device for information processing

An information processing device comprising:

• N, n-digit registers in a sequence R.sub.1, R.sub.2, R.sub.3, . . . R.sub.N, each of said registers having an input and an output;
• a respective input strobe circuit connected to the input of each register of said sequence from the second register R.sub.2 to the last register R.sub.N thereof, and a respective output strobe circuit connected to the output of each register of said sequence from the second register R.sub.2 to the last register R.sub.N thereof;
• a first information bus connected directly to the output of said first register R.sub.1 and to each of the input strobe circuits, and a second information bus connected directly to the input of said first register R.sub.1 of the sequence and to each of said output strobe circuits, each of said input strobe circuits transferring information signals to the respective register R.sub.2 . . . R.sub.N from said first bus and each of said output strobe circuits transferring information signals from the respective registers R.sub.2 . . . R.sub.N to said second bus upon the application of a control signal to a respective control input of the respective strobe circuit;
• respective first control lines to each of said registers of said sequence from the third register R.sub.3 to the last register R.sub.N of said sequence, each of said first control lines being connected to the control inputs of both the input and output strobe circuits of the respective register R.sub.3 . . . R.sub.N for direct control of transfer of information to and from the registers R.sub.3 . . . R.sub.N ;
• a second control line connected directly to the control input of the output strobe circuit of the second register R.sub.2 ;
• an OR-gate having its output connected to the control input of the input strobe circuit of the second register R.sub.2 and a first input connected to said second control line;
• and
• a third control line connected to a second input of said OR-gate whereby a signal applied to said third control line transfers the contents of said first register R.sub.1 to said second register R.sub.2 through said buses and signals applied to the respective lines effect parallel transfer of information between said registers.