Method of making buried channel charge coupled device with means for controlling excess charge

#This invention relates to a method of making charge coupled devices (hereinafter CCD's) of the type where excess charge is removed from the potential wells in a channel without spilling over to an adjacent well in that channel and, more particularly, to a method of making such devices with buried channels.

#CCD's are electronic devices that store and transfer charge along a channel. They generally include a semiconductor substrate over which is formed an insulating layer as well as parallel electrodes that extend over the layer in a direction generally transverse to the channels. Between the channels, there are provided channel stop diffusions that form potential barriers to confine the charge in its channel by preventing it from spilling over to the adjacent channel. The electrodes are used to control potential wells in the substrate adjacent each electrode. By sequentially applying clocking signals, charge can accumulate in these wells and can be transferred from one well to the next along an individual channel.

#One of the problems associated with CCD's is charge overload. For example, if the CCD is used in an image sensing array to store and transfer radiant energy and if an intense radiant energy source is imaged onto a particular well, the amount of charge generated at that location may be in excess of that which can be stored. This excess charge is prevented from leaving the channel because the surface potential created by the channel stop is lower than the surface potential between adjacent wells along a channel. Thus, the excess charge spills out of its potential well and into one or more adjacent wells in the same channel. This phenomena results in the spreading of any intense image read out of the array and is known as "blooming".

#FIG. 1-4 are section views illustrating a method of making a CCD in accordance with this invention; and

#FIG. 5 is a broken away perspective view of a charge coupled device made in accordance with the method of this invention.

#In FIG. 1 there is illustrated a body 10 of semiconductor material, for example silicon, on which is to be formed a buried channel CCD including buried N channel regions (shown generally at 24 in FIG. 5), channel stops (shown generally at 22 in FIG. 5) and excess charge drains (shown generally at 20 in FIG. 5). The device will be fully explained hereinafter. It should be understood that the CCD could be a P channel type device in which case all conductivity types described hereinafter would be reversed. Initially, the body 10 is a conventional silicon wafer uniformily doped with conductivity atoms of the P type. In the embodiment disclosed herein, the body 10 is doped with boron atoms in a concentration of about 10.sup.14 to 10.sup.15 atoms/cm.sup.3. On one major surface 12 of the body 10 there is deposited an oxide layer 14 having a thickness within a range of about 4800 to 5400 Angstroms. The oxide layer extends uniformly over the surface 12 and can be silicon dioxide (SiO.sub.2) thermally grown in an ambient of steam and hydrogen chloride (HCl) at a temperature of about 900.degree. C. for about 51/2 hours. After the oxide layer 14 is grown, its exposed surface is covered with a suitable masking layer 16. In carrying out a preferred embodiment of the invention, the layer 16 is a positive type photoresist applied with generally conventional techniques and processed in accordance with generally conventional photolithographic techniques to define protected and unprotected areas over the surface 12. The unprotected areas are located where the drains 20 of the device are to be formed. After photolithographic processing, openings 18 are etched in the areas of the oxide layer 14 adjacent the unprotected areas of the masking layer 16 to expose regions of the surface 12 where the drains 20 are to be formed. A conventional etchant such as a buffered hydrofluoric acid (HF) is used.

#After the openings 18 are formed, ion implantation techniques are used to deposit a heavy concentration of N type atoms through the openings into the exposed regions of the surface 12. Arsenic (As) is the preferred dopant material because of its relatively slow diffusion rate, but it should be understood that phosphorous or other suitable N type dopant could be used. The arsenic implantation energy is 200 KeV and the dose is 3.6.times.10.sup.14 atoms/cm.sup.2. Typically, the arsenic atoms are implanted to a depth of about 100 Angstroms below the surface 12 and have a concentration of about 7.times.10.sup.19 atoms/cm.sup.3. After the arsenic atoms are implanted, the drains 20 are formed as illustrated in FIG. 1 of the drawing.

#After the drains 20 are formed, the openings 18 in the oxide layer 14 are enlarged as shown at 18a in FIG. 2. Typically about 3 microns is added to each side of the opening 18. This is accomplished by etching back the oxide layer 14 around the opening 18. A suitable etchant such as buffered hydrofluoric acid is used for of about 20 minutes although it should be understood that the time depends on the size of the opening 18a. The hydrofluoric acid etches only the oxide layer 14, but does not etch the photoresist layer 16. It is believed that during the drain implant the arsenic or the phosphorous, if it is used, polymerizes or reacts with the photoresist to make it resistant to the etch. After the openings 18a are formed, the masking layer 16 is stripped from the oxide layer 14 and the body 10 is now ready for the formation of the channel stops 22 as illustrated in FIG. 3 of the drawing. Stripping of the photoresist 16 is done in a plasma etch for about 10 minutes. The plasma etch is necessary because the photoresist is otherwise difficult to remove after the implantation of the N type dopant. After the plasma etch, conventional cleaning techniques are used to remove any residue from the oxide layer 14.