US 4,361,949 AGranted

Process for making a memory device

AssigneeHitachi, Ltd.

InventorsRyoichi Hori, Masaharu Kubo, Norikazu Hashimoto, Shigeru Nishimatsu, Kiyoo Itoh

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Abstract

A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer. Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer. First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.

Claims25

Dependent claims

A process for making a multi-level electrode structure for a semiconductor device formed in a surface region of a single semiconductor substrate, comprising steps of:

forming a first conductive layer above a first part of the surface region of said substrate;
forming a first insulating layer on said first conductive layer;
forming a first opening in a first part of said first insulating layer;
forming a second conductive layer so that a first part of said second conductive layer overlies a second part of the surface region of said substrate and a second part of said first insulating layer, and so that a second part of said second conductive layer overlies a third part of said first insulating layer which is between said first and second parts of said first insulating layer, and so that a third part of said second conductive layer is connected with said first conductive layer;
removing said second part of said second conductive layer so that said third part of said second conductive layer is isolated from said first part of said second conductive layer;
forming a second insulating layer so that first and second parts of said second insulating layer respectively overlie said first and third parts of said second conductive layer;
forming second and third openings simultaneously in said first and second parts of said second insulating layer;
and
filling said second and third openings simultaneously, respectively, with first and second conductors so that said first and second conductors are connected with said first and third parts of said second conductive layer, respectively.

6 more elements

A process for making a multi-level electrode structure for a semiconductor device formed in the surface region of a semiconductor substrate comprising:

(a) forming a first electrode which is disposed above a semiconductor substrate surface, and then forming a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer;
(b) forming a second electrode which is made of a second conductive layer disposed above said substrate surface, at least a part of said second electrode overlying said first insulating layer at a position other than said first opening;
(c) forming a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode;
(d) forming a second insulating layer disposed on both said second electrode and on said subsidiary conductive layer;
(e) forming second and third openings simultaneously through the second insulating layer at respective predetermined positions above the second electrode and the subsidiary conductive layer;
(f) forming a first conductor disposed in said second opening and connected with said second electrode;
and
(g) forming a second conductor disposed in said third opening and connected with said subsidiary conductive layer, said second conductor forming an interconnection for said first electrode.

5 more elements

A process for making a semiconductor device having at least two semiconductor circuit elements formed on a single semiconductor substrate, comprising:

(a) a step of forming a first conductivity type semiconductor substrate which contains a first conductivity type active impurity;
(b) a step of forming a first field-effect circuit element in the surface region of said semiconductor substrate,
said step including forming a first gate insulating layer on a first part of the surface region of said substrate, forming a first gate electrode made of a first conductive layer on said first gate insulating layer, and forming a first inter-layer insulating layer on said first gate electrode;
(c) a step of providing a first penetrant opening in a first part of said first inter-layer insulating layer;
(d) a step of forming a second field-effect circuit element in the surface region of said semiconductor substrate and forming a subsidiary conductive layer in said first opening in a manner whereby said subsidiary conductive layer is connected with said first electrode and is isolated from said second electrode,
said step including forming a second gate insulating layer on a second part of the surface region of said substrate, and then forming simultaneously and of the same material said subsidiary conductive layer inserted into said first opening and a second gate electrode made of a second conductive material so that the first part of said second gate electrode overlies said second gate insulating layer and a second part of said second gate electrode overlies a second part of said first inter-layer insulating layer different from said first part of said first inter-layer insulating layer, said forming simultaneously and of the same material the subsidiary conductive layer and the second gate electrode comprising (d1) forming a conductive layer so that a first part of said conductive layer overlies said second gate insulating layer and said second part of said first inter-layer insulating layer, and so that a second part of said conductive layer overlies a third part of said first inter-layer insulating layer which is located between said first and second parts of said first inter-layer insulating layer, and so that a third part of said conductive layer is inserted in said first opening;
and (d2) removing said second part of said conductive layer so that said first part of said conductive layer forms said second gate electrode and said third part of said conductive layer forms said subsidiary conductive layer;
(e) a step of forming a second inter-layer insulating layer on said second gate electrode and on said subsidiary conductive layer;
(f) a step of forming second and third openings in said second inter-layer insulating layer simultaneously, said second and third openings respectively overlying said second gate electrode and said subsidiary conductive layer;
(g) a step of filling said second opening with a first conductor in a manner to be connected with said second gate electrode;
and
(h) a step of filling said third opening with a second conductor in a manner to be connected with said subsidiary conductive layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/269,507Filed 1 Jun 1981 · continuation in part
Priority: JP 52-226814 Mar 1977
Granted: 7 Dec 1982
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs