Digital synchronizing system

Abstract

A synchronizing system for the control of the transmission of digital information which is composed of blocks separated by gaps and for which synchronization requires the production of a reference pulse. Each field of information includes a series of spaced coded synchronizing control words each of which is a coded representation of the separation between the word and the position required for the synchronizing signal. The synchronizer (FIG. 3) includes a decoder composed of read-only memories (IC2, IC3) which can set a counter (IC4, IC5 and IC6) in accordance with the separation. The decoded synchronizing control signal is compared by comparator IC8 and a read-only memory IC7 with the instantaneous contents of the counter and the counter is adjusted only if parity is not detected. If parity is detected and continues to be detected for each synchronizing control word, the counter counts towards a datum whereupon the synchronizing signal is produced. The occasions of parity are counted by another counter which causes the production of an inhibiting signal for the output synchronizing signal unless a predetermined number of occasions of parity are counted.

Dependencies are inferred from the claim text.