Circuit arrangement for a radar for automatic recognition of moving targets
AssigneeSiemens Aktiengesellschaft
InventorRudolf Hauptmann
Life of this patent
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Abstract
A moving window detector for a radar including adding circuits for automatic detection of moving targets wherein the components of prior art devices are substantially reduced by utilizing a digital integration circuit and a shift register with a number of storage locations and wherein the input echo signals are supplied to the input of the shift register and to the integration circuit and the output of the shift register and the integration circuit are supplied to a subtracting circuit which supplies an output to an adder of the integration circuit so as to substantially reduce the number of components over those of the prior art.
Claims12
A moving window detector for radar comprising, an input terminal to which echo scan signals are supplied, an adder means connected to said input terminal, an individual storage means connected to said adder means, a shift register having a number of storage cells with its input connected to said input terminal, a subtractor which receives the outputs of said shift register and said individual storage means, and supplies an output to said adder means, and an output terminal connected to the output of said individual storage means.
A moving window detector for radar comprising, an input terminal to which echo scan signals are supplied, a subtractor means connected to said input terminal, an adder means connected to the output of said subtractor means, an individual storage means connected to said adder means and supplying a feedback signal from its output to said adder means, a shift register having a number of cells connected between said input terminal and said subtractor circuit and an output terminal connected to the output of said individual storage means.
A moving window detector for radar comprising an input terminal to which echo scan signals are supplied, an adder means connected to said input terminal, a subtractor means connected to the output of said adder means, an individual storage means connected to the output of said subtractor means and supplying an output to said adder means, a shift register with a number of storage cells connected to said input terminal and supplying an output to said subtracting means, and an output terminal connected to the output of said individual storage means.
A circuit arrangement for automatic recognition of moving targets employing a moving window detector in the form of a summing circuit, comprising an adder (ADD), an individual storage means (SP) connected to the output of said adder, an output terminal connected to said individual storage means, for the summation of m echo signals which succeed one another at the input of said adder (ADD) limited to a given number n by means including a delay shift register (SPK) which receives the input signal from an input terminal and has a given number n of storage locations, and a subtractor receives the outputs of said shift register and said individual storage means and supplying an input to said adder.
A circuit arrangement for automatic recognition of moving targets employing a moving window detector in the form of a summing circuit, comprising an adder (ADD), an individual storage means connected to the output of said adder and supplying an input to said adder, for the summation of m echo signals which succeed one another at the input of said adder (ADD) limited to a given number n by means including a delay shift register (SPK) which receives the input signal from an input terminal and has a given number n of storage locations, and a subtractor (SUB) connected to said input terminal and receiving the output of said shift register and supplying an input to said adder .
A circuit arrangement for automatic recognition of moving targets employing a moving window detector in the form of a summing circuit, comprising an input terminal, an adder (ADD) connected to said input terminal, a subtractor receiving the output of said adder, an individual storage means (SP) connected to receive the output of said subtractor and supplying an input to said adder, an output terminal connected to the output of said individual storage means, for the summation of m echo signals which succeed one another at the input of said adder (ADD) limited to a given number n by means including a delay shift register (SPK) which receives the input signal from said input terminal and has a given number n of storage locations, and the output of the shift register is connected to said subtractor (SUB).
Dependencies are inferred from the claim text.