Clocking system for a self-refreshed dynamic memory

A method for reading data stored in a memory cell of a self-refreshed dynamic semiconductor memory circuit including clocking circuitry wherein the memory cells are addressed using an address signal comprising the steps of:

• detecting a first address signal;
• generating a memory refresh signal in response to detection of the first address signal;
• applying the memory refresh signal to the semiconductor memory circuit for refreshing data stored in the memory cells of the semiconductor memory circuit;
• after applying the memory refresh signal to the semiconductor memory circuit, detecting a second address signal;
• applying the second address signal to the semiconductor memory circuit for accessing the second addressed memory cell to thereby read the data stored therein without generating an additional refresh signal;
• and
• resetting and precharging the clocking circuitry during application of the refresh signal to the semiconductor memory circuit.

A method for reading data stored in a memory cell and writing data into a memory cell of a self-refreshed dynamic semiconductor memory circuit wherein the memory cells are addressed for reading using an address signal and addressed for writing using a write-enable signal comprising the steps of:

• detecting the write-enable signal;
• writing data into a memory cell of the semiconductor memory circuit;
• after writing data into the enabled memory cell, applying the memory refresh signal to the semiconductor memory circuit;
• detecting an address signal;
• and
• applying the address signal to the semiconductor memory circuit for accessing the addressed memory cell to thereby read the data stored therein without refreshing the memory circuit such that the refresh after the write cycle is shared with the memory access.