Decoder circuit for semiconductor memory

A decoder circuit for transmitting a row enable signal to a row line of a semiconductor memory in response to receipt of a row address signal which is transmitted through a plurality of address lines as first and second voltage states, the circuit functioning during each memory cycle in response to at least one precharge signal followed by an address enable signal, the decoder circuit, comprising:

• means for precharging a first node to said second state in response to said precharge signal;
• means for driving said first node to said first state upon receipt of said address signal when said received address signal has said first state on at least one of said address lines;
• means for connecting said first node to a second node in response to said address enable signal during receipt of said address signal, said second node receiving the state of said first node, and for disconnecting said first node from said second node after receipt of said row address signal to trap the state of said second node thereon;
• means for precharging a third node to said first state in response to a precharge signal;
• means for driving said third node to said second state when said first state is trapped on said second node and for maintaining said first state on said third node when said second state is trapped on said second node;
• and
• means for transmitting said row enable signal to said row line when said third node is at said first state.

A decoder circuit for transmitting a row enable signal to activate a row line of a semiconductor memory in response to an address supplied through a plurality of address lines, the decoder circuit functioning in response to at least one precharge signal and an address enable signal, the circuit powered through first and second power terminals, comprising:

• a plurality of input transistors having the drain terminals thereof connected to said first power terminal, the source terminals thereof connected to a first node and each gate terminal thereof connected to a respective one of said address lines;
• a first transistor having the drain terminal thereof connected to said first node, the source terminal thereof connected to said second power terminal and the gate terminal thereof connected to receive a precharge signal;
• a second transistor having a first of the drain and source terminals thereof connected to said first node and the remaining one of the drain and source terminals thereof connected to a second node and the gate terminal thereof connected to receive said address enable signal;
• a third transistor having the drain terminal thereof connected to a third node, the source terminal thereof connected to said second power terminal and the gate terminal thereof connected to said second node;
• a fourth transistor having the drain terminal thereof connected to said first power terminal, the source terminal thereof connected to said third node and the gate terminal thereof connected to receive a precharge signal;
• and a fifth transistor having the drain terminal thereof connected to receive said row enable signal, the source terminal thereof connected to said row line and the gate terminal thereof connected to said third node.

A decoder circuit for transmitting a row enable signal to activate a row line of a semiconductor memory in response to an address supplied through a plurality of address lines, the decoder circuit functioning in response to at least one precharge signal, the decoder circuit powered through first and second power terminals, comprising:

• a plurality of input transistors having the drain terminals thereof connected to said first power terminal, the source terminals thereof connected to a first node and each gate terminal thereof connected to a respective one of said address lines;
• a first transistor having the drain terminal thereof connected to said first node, the source terminal thereof connected to said second power terminal and the gate terminal thereof connected to receive said precharge signal;
• a second transistor having the drain terminal thereof connected to a second node, the source terminal thereof connected to said second power terminal and the gate terminal thereof connected to said first node;
• a third transistor having the drain terminal thereof connected to said first power terminal, the source terminal thereof connected to said second node and the gate terminal thereof connected to receive a precharge signal;
• and
• a fourth transistor having the drain terminal thereof connected to receive said row enable signal, the source terminal thereof connected to said row line and the gate terminal thereof connected to said second node.

A method for decoding multi-bit address data in a semiconductor memory having row and column lines, the method comprising the steps of:

• transmitting row selection address bits through a group of address lines to an OR gate, each of said address lines connected to a respective input terminal of said OR gate;
• generating a first state at the output terminal of said OR gate when said OR gate is selected by the address bits received at the input terminals thereof;
• transmitting column selection address bits through said address lines after transmission of said row selection address bits therethrough;
• and
• inhibiting the output signal from said OR gate from changing state at the time of receipt of said column selection address bits at the input terminals of said OR gate.

A method for decoding a row address signal to select a row line in a semiconductor memory where the address signal is transmitted through address lines and is valid for a limited time period, comprising the steps of:

• precharging the output terminal of an OR gate such that the output signal from said OR gate is at a first state,
• transmitting said address signal through said address lines to respective input terminals of said OR gate;
• holding the output signal from said OR gate at said first state when said OR gate is selected by said address signal;
• driving said output signal of said OR gate to a second state when said OR gate is not selected by said address signal,
• gating the output signal of said OR gate through a pass transistor which is rendered conductive during said time period for transmitting the output signal of said OR gate to the input terminal of an inverter;
• driving said pass transistor nonconductive after receipt of said address bits at the input terminals of said OR gate to trap the state of the output signal of said OR gate on the input terminal of said inverter;
• and
• coupling the output signal from said inverter to a row driver transistor for controlling the conductivity thereof, said row driver transistor connected to said row line.

A method for decoding a row address signal to select a row line in a semiconductor memory where the address signal is transmitted through address lines and is valid for a limited time period, comprising the steps of:

• precharging the output terminal of a dynamic OR gate such that the output signal from said OR gate is at a first state,
• transmitting said address signal through said address lines to respective input terminals of said dynamic OR gate;
• holding the output signal from said OR gate at said first state when said dynamic OR gate is selected by said address signal;
• driving said output signal of said dynamic OR gate to a second state when said dynamic OR gate is not selected by said address signal,
• gating the output signal of said OR gate through a pass transistor which is rendered conductive during said time period for transmitting the output signal of said dynamic OR gate to the input terminal of a dynamic inverter;
• driving said pass transistor nonconductive after receipt of said address bits at the input terminal of said dynamic OR gate to trap the state of the output signal of said OR gate on the input terminal of said inverter;
• and
• coupling the output signal from said inverter to a row driver transistor for controlling the conductivity thereof, said row driver transistor connected to said row line.

A method for transmitting a row enable signal to a row line of a semiconductor memory in response to receipt of a row address signal which is transmitted through a plurality of address lines as first and second voltage states, the method operating in response to a precharge signal and a row address enable signal, comprising the steps of:

• precharging a first node to said second state;
• driving said first node to said first state upon receipt of said first state or any one of said address lines;
• connecting said first node to a second node in response to said row address enable signal, said second node charged to the state of said first node, and for disconnecting said first node from said second node after receipt of said row address signal to trap the state of said second node thereon;
• precharging a third node to said first state in response to a precharge signal;
• driving said third node to said second state when said first state is trapped on said second node and maintaining said third node at said first state when said second state is trapped on said second node;
• and
• transmitting said row enable signal to said row line when said third node is at said first state.