Memory cell comprising tunnel diodes and field effect transistors

An array of static memory cells, each cell comprising a tunnel diode inserted between a supply voltage and a first circuit, said supply voltage not much larger than the voltage drop across said tunnel diode pertaining to valley current flow so that the current through said tunnel diode when operating outside the tunnel regime never exceeds significantly the valley current, a variety of currents through said first circuit in response to sets of voltage signals applied at said first circuit through two circuit lines commonly referred to as word and bit lines, a first set of said signals such that the corresponding current withdrawn through said first circuit from the node between said tunnel diode and said first circuit is larger than the peak current of said tunnel diode, a second set of said signals such that the corresponding current through said first circuit is less than the valley current of said tunnel diode, the current through said first circuit being less than said peak current but higher than said valley current for any said set of voltage signals other than said first and second sets, a second circuit connected to said node between said tunnel diode and said first circuit, the impedance of said second circuit depending on voltage signals applied at said second circuit from said word and bit lines, said second circuit conducting only when a third set of said signals is applied, but non-conducting for any other set of said signals, the current through said conducting second circuit indicative of the voltage across said tunnel diode, thereby providing a read-out of the logic state of the memory cell, said first and second circuits comprsing field effect transistors.