US 4,360,891 AGranted

Address and data interface unit

AssigneeSperry Corporation

InventorsMichael H. Branigin, Ladislaw D. Cubranich, Edward E. Henderson

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Abstract

A large scale integrated circuit is designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. A key feature of the device is that it generates error correcting code parity bits on a byte wide basis so that ECC check bits for a multi-byte word can be generated externally with a minimum of hardware, and includes circuitry responsive to an error syndrome for correcting a single error within a byte. Data manipulation capabilities include standard logical operations, single bit shift operations, binary 2's complement arithmetic addition and subtraction, and decimal addition and subtraction. In addition, an input data byte on any bus can be passed unaltered or inverted to any other bus. The device is capable of receiving operands from one or two of three bidirectional data buses, performing a desired arithmetic or logical operation on the operand or operands, and returning the result to any one of the bidirectional buses including one which may have supplied one of the operands. An instruction is decoded at the leading edge of a clock pulse, and executed during the clock pulse. The result is entered into a result register on the trailing edge of the clock pulse so that that result is available to any bus during the same microcycle the instruction and operands are received.

An integrated circuit chip adapted for connection to external means including an instruction bus on which instructions appear, a source producing a clock pulse, a function modifier control line on which function modifier signals appear, and at least one data bus, said integrated circuit chip including thereon:

instruction decoder means for receiving an instruction from said instruction bus, a clock pulse from said source, and a signal on said function modifier control line, said instruction decoder means being responsive to the leading edge of said clock pulse for producing control signals during said signal pulse;
a result register having an output;
an arithmetic logic unit having an output connected to said result register for performing an Exclusive-Or function on signals applied thereto;
means for connecting the output of said result register to a first input of said arithmetic logic unit;
error syndrome decoder means connected between said data bus and a second input of said arithmetic logic unit;
said instruction decoder means including first means responsive to a predetermined instruction on said instruction bus and the presence of a signal on said function modifier control line for controlling said error syndrome decoder means to decode an error syndrome on said data bus;
said instruction decoder means including second means responsive to said predetermined instruction on said instruction bus and the presence of a signal on said function modifier control line for controlling said arithmetic logic unit to take the Exclusive-Or of said decoded error syndrome and the output from said result register;
said result register being responsive to the trailing edge of said clock pulse for receiving the output of said arithmetic logic unit;
said instruction decoder means includes third means responsive to said predetermined instruction and the absence of a signal on said function modifier control line for inhibiting operation of said error syndrome decoder means whereby said error syndrome decoder means produces a zero value output;
and
said instruction decoder means including fourth means responsive to said predetermined instruction and the absence of a signal on said function modifier control line for controlling said arithmetic logic unit to perform the Exclusive-Or function on said zero value and the output of said result register.

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Abstract

Claims8