Semiconductor device having an improved multilayer wiring system

A semiconductor device having a semiconductor body including an integrated circuit having a plurality of semiconductor circuit elements adjacent the surface of said body, which comprises:

• a first electrically insulating layer adjacent the surface of said semiconductor body, portions of said first insulating layer serving to laterally isolate adjacent circuit elements;
• a first metallization pattern which is sunken into a portion of the first insulating layer through only a part of the thickness of said first layer, the surface of said first metallization pattern substantially coinciding with that of the first layer and said circuit elements;
• a second electrically insulating layer overlying said first layer, the first metallization pattern sunken therein and portions of said circuit elements;
• and
• a second metallization pattern on said second layer, overlying said first pattern and being separated therefrom by said second layer, the second metallization pattern contacting at least one region of at least one of said semiconductor circuit elements through a contact hole in the underlying second layer.