US 4,360,788 A · Phase-locked loop frequency synthesizer

Abstract

A programmable divide-by-N phase-locked loop having a pulse incrementor circuit and a single sideband mixer circuit embedded in the loop feedback path is disclosed. In each disclosed arrangement, one input port of the single sideband mixer receives the signals supplied by the phase-locked loop voltage controlled oscillator and, depending upon whether the mixer employed is configured for supplying an upper sideband signal or a lower sideband signal, either increases or decreases the frequency of the phase-locked loop feedback signal by a factor f.sub.s, where f.sub.s is the frequency of a control signal applied to the second input port of the signal sideband mixer. The pulse incrementor circuit receives the signal supplied by the single sideband mixer and, depending on whether the pulse incrementor is configured for deleting signal pulses or adding signal pulses, either decreases or increases the average frequency of the signals supplied to the phase-locked loop programmable divider by a factor f.sub.d, where f.sub.d is the frequency of a control signal applied to the pulse incrementor. Since the phase-locked loop synchronizes or locks when the phase of the signal supplied by the programmable divider is equal to the phase of a reference frequency f.sub.r, which is supplied to the phase-locked loop phase detector, the arrangement causes the phase-locked loop voltage controlled oscillator to supply a signal at a frequency of Nf.sub.r .+-.f.sub.d .+-.f.sub.s, where N is the selected divisor of the phase-locked loop programmable divider and the operations of addition and subtraction are determined by the type of single sideband mixer and pulse incrementor utilized. To suppress spurious output signals, both control frequencies f.sub.d and f.sub.s are maintained substantially above the phase-locked loop cutoff frequency. Separate pulse incrementor circuits for pulse deletion and pulse addition are disclosed, along with a combined pulse deletor programmable divider which utilizes variable modulus prescaling techniques.

Claims20

Dependent claims

In a frequency synthesizer system of the phase-locked loop variety wherein an output signal is supplied by a first voltage controlled oscillator, said output signal having a frequency determined by an error signal supplied to said first voltage controlled oscillator by a first phase detector circuit, said first phase detector circuit being responsive to an applied signal at a predetermined frequency f.sub.r and being responsive to a feedback signal derived from said output and having a frequency mathematically related to the frequency of said output signal, and wherein the apparatus for supplying said feedback signal includes a programmable frequency divider having an output terminal connected for supplying said feedback signal to said first phase detector, said programmable frequency divider for dividing the frequency of an applied signal by an integer N, said integer N being programmable between upper and lower limits that control said frequency of said output signal in incremental frequency steps equal in magnitude to said predetermined frequency f.sub.r, an improvement for controlling said frequency of said output signal in incremental frequency steps of a magnitude less than f.sub.r, said improvement comprising:

single sideband mixing means responsive to said output signal and responsive to an applied signal having a selectable frequency f.sub.s that exceeds the cutoff frequency of said phase-locked loop, said single sideband mixing means supplying a signal having a frequency substantially equal to said frequency of said output signal offset by an amount substantially equal to said selectable frequency f.sub.s ;
and,
frequency incrementing means responsive to said signal supplied by said single sideband mixing means and responsive to an applied signal having a selectable frequency f.sub.d that exceeds the cutoff frequency of said phase-locked loop, said frequency incrementing means including means for supplying a signal at a frequency substantially equal to said frequency supplied by said single sideband mixing means offset by an amount substantially equal to said selectable frequency f.sub.d to said programmable frequency divider.

A frequency synthesizer system for supplying an output signal at a selectable frequency f.sub.v =Nf.sub.r .+-.f.sub.d .+-.f.sub.s, where N is a selectable integer, f.sub.r is the frequency of an applied reference signal and f.sub.d and f.sub.s are respectively the frequencies of first and second applied control signals, each of said frequencies f.sub.d and f.sub.s being selectable from a plurality of signal frequencies, said frequency synthesizer system comprising:

controlled oscillator means, said controlled oscillator means responsive to an applied error signal for supplying the output signal of said frequency synthesizer system at a frequency determined by said error signal;
single sideband mixing means responsive to said signal supplied by said controlled oscillator means as said output signal of said frequency synthesizer system, said single sideband mixing means further responsive to said first applied control signal at said frequency f.sub.s, said single sideband mixing means including means for supplying a signal at a frequency substantially equal to f.sub.v .+-.f.sub.s ;
pulse incrementor means responsive to said signal supplied by said signal mixing means and responsive to said second applied control signal at said selectable frequency f.sub.d, said pulse incrementor means supplying a signal at a frequency substantially equal to f.sub.v .+-.f.sub.s .+-.f.sub.d ;
frequency divider means responsive to said signal supplied by said pulse incrementor means, said frequency divider means being programmable to supply a signal at a frequency substantially equal to (f.sub.v .+-.f.sub.s .+-.f.sub.d)/N, where N is said selectable integer;
phase detector means responsive to said signal supplied by said frequency divider means and responsive to said applied reference signal at said frequency f.sub.r, said phase detector means including means for supplying said error signal with a magnitude proportional to the difference between the phase of said signal supplied to said phase detector means by said frequency divider means and the phase of said reference signal at said frequency f.sub.r ;
and,
means for maintaining of said frequency f.sub.s and said frequency f.sub.d greater than the cutoff frequency of the phase-locked loop defined by said controlled oscillator means, said frequency divider means and said phase detector means.

4 more elements

A frequency synthesis system for supplying an output signal at a signal frequency that is selectable from a plurality of signal frequencies, said frequency synthesis system comprising:

phase detector means responsive to an applied reference signal having a predetermined frequency and responsive to a first applied system signal, said phase detector means for supplying an error signal, said phase detector means including means for establishing said error signal directly proportional to the difference in signal phase between said applied reference signal and said first system signal;
controlled oscillator means responsive to said error signal for supplying a signal as said frequency synthesizer output signal, said controlled oscillator means including means for varying the frequency of said supplied signal in proportion to the magntiude of said error signal;
single sideband mixer means responsive to a first control signal having a selectable frequency and responsive to said signal supplied by said controlled oscillator means, said signal sideband mixer means for supplying a signal having a frequency substantially equal to the difference between the frequency of said signal supplied by said control oscillator means and said selectable frequency of said first control signal;
signal processing means, said signal processing means responsive to said signal supplied by said single sideband mixer means and responsive to a second control signal having a selectable frequency, said signal processing means including means for supplying said first system signal to said phase detector means at a frequency substantially equal to the quotient of the difference between the frequency of said signal supplied by said single sideband mixer means and said selectable frequency of said second control signal divided by a selectable integer N;
first signal supply means for supplying said first control signal at a frequency greater than K.sub.p K.sub.v /N where K.sub.p denotes the coefficient of said phase detector means that relates said difference in signal phase to said error signal and K.sub.v denotes the coefficient of said controlled oscillator means that relates the frequency of the signal supplied by said controlled oscillator means to said error signal;
and,
second signal supply means for supplying said second control signal at a frequency greater than K.sub.p K.sub.v /N.

4 more elements

A frequency synthesis system for supplying an output signal at a signal frequency that is selectable from a plurality of signal frequencies, said frequency synthesis system comprising:

phase detector means responsive to an applied reference signal having a predetermined frequency and responsive to a first applied system signal, said phase detector means for supplying an error signal, said phase detector means including means for establishing said error signal directly proportional to the difference in signal phase between said applied reference signal and said first system signal;
controlled oscillator means responsive to said error signal for supplying a signal as said frequency synthesizer output signal, said controlled oscillator means including means for varying the frequency of said supplied signal in proportion to the magnitude of said error signal;
single sideband mixer means responsive to a first control signal having a selectable frequency and responsive to said signal supplied by said controlled oscillator means, said single sideband mixer means for supplying a signal having a frequency substantially equal to the sum of the frequency of said signal supplied by said controlled oscillator means and said selectable frequency of said first control signal;
signal processing means, said signal processing means responsive to said signal supplied by said single sideband mixer means and responsive to a second control signal having a selectable frequency, said signal processing means including means for supplying said first system signal to said phase detector means at a frequency substantially equal to the quotient of the sum of the frequency of said signal supplied by said single sideband mixer means and said selectable frequency of said second control signal divided by a selectable integer N;
first signal supply means for supplying said first control signal at a selectable frequency that exceeds K.sub.p K.sub.v /N where K.sub.p denotes the coefficient of said phase detector means that relates said difference in signal phase to said error signal and K.sub.v denotes the coefficient of said controlled oscillator means that relates the frequency of the signal supplied by said controlled oscillator means to said error signal;
and,
second signal supply means for supplying said second control signal at a selectable frequency that exceeds K.sub.p K.sub.v /N.

4 more elements

Dependencies are inferred from the claim text.

Phase-locked loop frequency synthesizer

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Phase-locked loop frequency synthesizer

Life of this patent

Abstract

Claims20